JPS6148378U - - Google Patents

Info

Publication number
JPS6148378U
JPS6148378U JP13233084U JP13233084U JPS6148378U JP S6148378 U JPS6148378 U JP S6148378U JP 13233084 U JP13233084 U JP 13233084U JP 13233084 U JP13233084 U JP 13233084U JP S6148378 U JPS6148378 U JP S6148378U
Authority
JP
Japan
Prior art keywords
signal
circuit
sample
counting
predetermined period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13233084U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13233084U priority Critical patent/JPS6148378U/ja
Publication of JPS6148378U publication Critical patent/JPS6148378U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1,2図は、それぞれこの考案の信号レベル
測定器の一実施例を示す回路構成図及び回路各部
の信号波形図である。 1……信号レベル測定器、2……サンプルホー
ルド回路、4……制御装置、8……計数回路、9
……ゲート回路。
1 and 2 are a circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing an embodiment of the signal level measuring device of this invention. DESCRIPTION OF SYMBOLS 1... Signal level measuring device, 2... Sample hold circuit, 4... Control device, 8... Counting circuit, 9
...gate circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同期信号が挿入された被測定信号が供給され、
外部からの制御信号によりサンプルホールドを行
なうサンプルホールド回路と、前記被測定信号中
の同期信号によりトリガされ、所定周期のクロツ
ク信号を計数する計数回路と、この計数回路の計
数出力があらかじめ設定した所定値に達したとき
に、前記サンプルホールド回路に対し制御信号を
供給するゲート回路とから構成してなる信号レベ
ル測定器。
A signal under test with a synchronization signal inserted is supplied,
A sample and hold circuit performs sample and hold based on an external control signal, a counting circuit that is triggered by a synchronization signal in the signal under test and counts clock signals of a predetermined period, and a counting output of this counting circuit that performs sampling and holding at a predetermined period. and a gate circuit that supplies a control signal to the sample and hold circuit when the signal level measuring device reaches a certain value.
JP13233084U 1984-08-31 1984-08-31 Pending JPS6148378U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13233084U JPS6148378U (en) 1984-08-31 1984-08-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13233084U JPS6148378U (en) 1984-08-31 1984-08-31

Publications (1)

Publication Number Publication Date
JPS6148378U true JPS6148378U (en) 1986-04-01

Family

ID=30690896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13233084U Pending JPS6148378U (en) 1984-08-31 1984-08-31

Country Status (1)

Country Link
JP (1) JPS6148378U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5575655A (en) * 1978-12-01 1980-06-07 Hitachi Ltd Waveform analyzer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5575655A (en) * 1978-12-01 1980-06-07 Hitachi Ltd Waveform analyzer

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