JPH0212765U - - Google Patents

Description

[Brief explanation of drawings]

1 to 4 show an embodiment of the error rate counter for DAT according to this invention, FIG. 1 is a block diagram of the main part, FIG. 2A is a timing chart of SWP, and FIG. 2B is MNTG. A timing chart showing the output timing of MNT, Figure 2C is
Figure 2D is an enlarged view of G, Figure 2D is a timing chart of error data synchronized with MNTG, Figure 3 is a memory map showing the state in which error data is stored in memory, and Figure 4A is the flow of the main routine of the microcomputer. FIG. 4B is a flowchart of the microcomputer interrupt routine. FIG. 5 is a block diagram showing a conventional embodiment. Explanation of main symbols, 1...Data input terminal, 2...
...MNTG input terminal, 3...SWP input terminal, 6
...One shot multivibrator, 7...Latch, 8...CPU board, 9...Interrupt input terminal, 10...PCM/SUB selection switch, 1
1...Sampling switch, 17, 18...L
ED display, 19, 20...Cuse segment decoder/driver, 21...I/O board, 22, 2
3...D/A converter and amplifier, 24...Good/failure indicator.

Claims (1)

[Scope of Claim for Utility Model Registration] In an error rate counter for DAT which is configured to import error data into a microcomputer in synchronization with a monitor trigger timing pulse and measure an error rate, the error rate counter may be set to 1 in response to input of the monitor trigger timing pulse. A one-shot multivibrator that outputs two pulses and a latch that holds the error data using the output pulse of this one-shot multivibrator are provided, and the output pulse of the one-shot multivibrator is input to the interrupt input terminal of the microphone computer. An error rate counter for a DAT, characterized in that the error data held in the latch is input to a microcomputer based on the output pulse of the one-shot multivibrator.