JPS6146623A - Coding and decoding method - Google Patents

Abstract

PURPOSE:To attain error detection with the same method as that for a 2-element code and the same correcting capability by using a 2-element shift register to generate elements of GF(2<m>) so that the elements are common to those of a code C2. CONSTITUTION:In selecting a code C1 as a 2-element code and selecting a generation polynomial as G(X)=(X<8>+1).(X<8>+X<4>+X<3>+X<2>+1), this results in selecting a generation polynomial G(X)=(X+1).(X+alpha<8>) in a Galois field GF(2<m>), then when it is designed that a syndrome operation of C2 decoding includes S(alpha<0>), S(alpha<8>), the syndrome operation crcuit for C1, C2 is used in common. In order that roots alpha<i>, alpha<i+l>, alpha<i+2l> of the C2 code include the roots of the C1 code, it has only to arrange the difference of the power of each root (alpha) at an equal interval.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an error correction code, and particularly relates to an encoding/decoding method thereof.

[Conventional technology]

FIG. 1 is an explanatory diagram of a decoder that decodes double codes. In the figure, (1) is the information input terminal, (2) is the output terminal, and (3
) is a C1 decoder, and (4) is a C2 decoder. In this example, C1 is (n + , ni + , d I) binary code, (
For example, CRC (Cyc Redundant)
cy Check) code C2 (n2. to 2.d2).

The information input from the input terminal is encoded with R3 (Reed-3 olomon) code, and the syndrome is calculated by a binary code serial shift register, error detected or corrected, and output to the C2 decoder, where the error is again detected. The corrected data is output from the output terminal (2). Here, the (n, k, d) code is a linear code with code length n, number of information symbols k, and minimum distance 11Jlid. In this case, the C1 code is a binary code, so if it is used only for error detection, it can be configured with n+- and + stage shift registers, but since it is a binary code, the hardware is more complex than an R8 code etc. Since the number of error bits that can be corrected is small, it is not particularly effective against burst errors.

FIG. 2 shows another conventional example in which 15) uses a C1 code in an RS decoder. In this case, if the Galois fields GF (2m) of codes C1 and C2 were made the same field, a considerable part of the hardware including the syndrome calculation circuit could be made common. However, in this case, even if an attempt was made to use the C1 code only for detection, it could not be constructed with a single-stage shift register as in the old case, and required hardware of approximately the same level as a syndrome calculation circuit.

Here, an example will be shown in which the binary code and the code on GF(2m) are different.

The conventionally known code on G F +21 is:
For example, CRCC (Cyclic Redundancy)
y Check Code). As an example, FIG. 8k shows the encoding device. The generating polynomial G1(x) of this CRCC is the following formula% formula% In the figure, (6) is the input terminal (7) of the information data,
Control signal input terminal, [81+9+ GO)
fill (121en05) (161119(+81
119) t20+ (22) U 0 slope (to) is a 1-bit register, 11J and D (branch)) is a 1-bit addition circuit modulo 2. The amount is an AND gate, the track is a selector, and the group is a sign output terminal. be. Here, the information data is 1 bit, the first data is 1-1 Ck+, x, and the last data is C+ (Ck+,
Ck+-+"3.

When C1 is expressed as a coefficient of 1 or O), it can be regarded as a polynomial of X. Multiply nl- with a code length of n1 bits by +, and multiply the information data polynomial M(x) by X,
Dividing this by the generator polynomial G1(x) gives
It becomes 1. Here, Q (X) is the quotient and R(x) is the remainder. Therefore, n+ − + U (x) = x MX)+・R(X)・Q
(X)c I(X)...+31, where U (x) is a sign, the upper 1 bit is information data, and the lower n + -k
The + bit represents test data R(x).

Figure 8 shows the case where +=16 for n+-,
While the signal from input terminal 2 is % I N, A of □□□
ND gate opens and 1 bit register +81 +91
GO) fill +121 Il& +15) (1
61uTr +181 +191 bite @ (231(2
41a C7) Data and addition circuit □ 1131111
(7) The division in equation (2) is executed based on the output. The selector (support) selects information data from the input terminal (6).

When the k1-bit information data has been input, the input terminal (7
) becomes 90'', the AND gate (2) closes, and the next n+ -k + (=16) bits of data in the listening register are sequentially sent to the selector, and the output terminal (
b) is output.

As an example, old = 282. If +=216 and 8 bits of '00000001' are repeatedly used as information data, the test data R(x) becomes '0000100010111101'.

When decoding, division is performed by setting the signal at the input terminal (7) to 11'' for n bits, and if there is no error, all the data in each register becomes 50''.

As described above, CRCC has the feature that it can be calculated bit serially.

On the other hand, a conventionally known code on GF (2m) is the Reed-3o Lomon code (hereinafter referred to as R8 code). Here, in order to correspond with CRCC, G
Consider F(2) above. Code length N, information length k, minimum distance (g), k, D) as R3 code (29, 27, 8)
Taking the R3 code as an example, when considered bit serially, n
+=8XN, and +=8XK. (29, 27
, 8) The generating polynomial G + (x) of the R8 code is G1(x) = (x・a) = x 10a x
・H・・(Given by 4+. Here α is G F L2
An 8th degree primitive polynomial on
x +1).

FIG. 4 shows an example of the encoding device. In the figure, 廀 is an input terminal for information data, (31) is an input terminal for control signals, □□□ (33) is a multiplier on GF (2), (g) ■ is an 8-bit register, (g) 8) is an 8-bit modulo-2 addition circuit, (39) is an AND gate, and (4o) is a selector t41) is a code output terminal. If the preliminary report data is M (x), then xN・KM'(X)=Q'(x)G1(x)+R'(x
)...5] l) U (X) is the sign. Since the calculation is performed using GF(2), the method of representing the Galois field element will be explained first. Primitive polynomial X 10x +x 10x
−H=o root is α, α is (00000010) and 2
When expressed in base numbers, α, α, . . . are as follows.

α 255−α8 This original representation method will be referred to as "vector representation" here. A list of vector expressions is shown in Table 1. In addition, the table of values when the vector expression is a number is called "logarithmic expression".
I will call it.

Encoding is performed by the encoding apparatus shown in FIG. 4 using the elements on GF(2) as described above. 8-bit parallel information data is input from the input terminal (30). The control signal from the input terminal (31) remains at 11" until the information data is input, and the control signal from the multiplier (32) (331 (
341, an 8-bit register (t) +37), and addition circuits +36+ and +38+ execute the division in equation (5). Here, (32)C33)'2Ai is a multiplier that multiplies the input data by α (-α), α, and α, respectively. The controller (40) selects the information data from the input terminal 25 and outputs it to the output terminal (4 degrees Celsius).When the division of K pieces of information data is completed, the control signal from the input terminal (31) is " 0” and becomes an 8-bit register!35)
Select the output of ((capital) with the selector 85 and output terminal 141.
).

As an example, N=29. = 27 and all information data is C0 (-ooooooooi), inspection data R(x
) is α”5 (=OO000011), α (=O
OOOOO10).

The bit serial order of R'(i) is the inspection data R(X) calculated by CRCC (=OOOO1000
10111101) does not match.

In this way, k, conventional GF (21) and GF (2
”) When the above codes were arranged in bit serial, the test data did not match even if the code length and information length were the same.

Therefore, there is a drawback that it is difficult to decode a bit-serial code into m-bit parallel code, or vice versa. Another drawback is that it is not possible to perform error correction on the R8 code on GF (2rrl) in bit serial and check j, , m bits in parallel.

[Summary of the invention]

The present invention has been made with the aim of eliminating this conventional problem.When 01 is used only for detection, it is composed of an n+-k+ stage shift register, and when executing 01 correction, it is composed of a shift register of n+-k+ stages.
It has a structure that can be used in common with hardware for binary codes, and its correction ability is completely the same as that of R3 codes, and it is characterized by being able to detect errors using the same method as binary codes.

[Embodiments of the invention]

An embodiment of this invention will be described below.

First, as a C1 code, (282
, 216) on binary code and GF(2) (29,
27.8) Explain R8 code. The first term (x + 1) on the right side of equation (7) corresponds to the first term (x + 1) on the right side of equation (8), and the second term (x8
-1-x'+x8+x2+1) corresponds to the second term (X10α8) on the right side of equation (8). In other words, equation (7) on G F +21 and equation (8) on GF (28) can be considered to be the same. This can be understood from the fact that the first term on the right side of equation (7) represents parity, and the second term is the primitive polynomial of α in equation (8). An apparatus for bit-serial encoding of this code is shown in FIG. 5k, and an apparatus for encoding this code in 8-bit parallel is shown in FIG. First, a device for bit serial encoding will be explained. In Figure 5, (
42 is an information data input terminal, (43) is a control signal input terminal, (441C45) (4n (49)
(51) (52) U)EA (55) 156+
U) +601 (G21 (1(49) C65)
fly bit register, 1461 f4a (5fll
(57) 691 (fill +66) is a 1-bit adder modulo 2, dawn is an AND gate, (68) is a selector, and (69) is a code output terminal. Input terminal (4
The information data of Zr and the control signal of the input terminal (43) are the same as those shown in FIG.

(282, 216) The test data in the binary code is “1”
011100110111000".

On the other hand, in FIG. 6, aO) is an input terminal for information data, C1) is an input terminal for control signals, and ff21 (
73) (7Φ is α , α , α multiplier, C
5) (capital) is an 8-bit register, (76) C781 is 2
8-bit adder modulo, ff9) is an AND gate,
(Head is a selector, +76) is an output terminal. The information data of the input terminal (70) and the control signal of the input terminal (-) are the same as those corresponding to FIG. 4. (2
9,27) The test data in R3 code are α, α
becomes. α =ゝ10111001"α182='
10111000'', the (29, 27) R3 code arranged bit serially from the MSB side completely matches the one obtained in FIG.

Next, the decoder will be explained. If you only want to check whether there is an error in the received code, you can perform division including the test data in Figures 5 and 6, and check whether the data in each register is all 10''. .

FIG. 7 shows an example of a decoding circuit, in which (1) is an information input terminal;
(2) is the information output terminal, (811 is the syndrome SO calculation circuit, 唖 is the syndrome 88 calculation circuit, 匈) is the division circuit, (841 is the logarithm ROM memory, (851 is the 178
Multiplier, (86) is the error position register, □□□ is the error pattern register, (the figure is the error correction circuit, (8 mark is the delay circuit, the picture is the S4 syndromic check circuit, +91
1 is an error detection terminal.

Here, the parameters of code C+ and C2 are (10, 8, 8
) , (10, 7, 4).

In the conventional method, the syndrome calculation for C1 decoding is 1=O, where α is the primitive polynomial x 10x 10x +x +1=O
It is the root of

C2 decoding syndrome is SO=Σri i=0 9.1 Sl−Σr1α i=.

Therefore, the syndrome calculation circuits So and S+ can be shared.

However, this eliminates the advantage of using a binary code as the 01 code like CRC, which allows easy encoding and decoding with a serial shift register. By generating the element of GF(2m) with a binary shift register and devising a way to make the element common to the element of code C2, the C1 code can be made like a binary code or like an R3 code. It is an object of the present invention to encode and decode the data. Let C1 be a binary code, and use the generator polynomial as G (x)= (x +t) (x + x
If we choose 10x +x +1), this becomes Galois field GF (2
Generator polynomial Qx)-(X+1) (X0α
), so if you design the syndrome calculation for C2 decoding to include S(α) and S(α), CI
, C2 syndrome calculation circuit i i+l i
+l power.

can be shared. In order to include the roots α, α, and αC1 of the C2 code, the differences in the powers of α of the respective roots may be arranged at equal intervals.

That is, in this case, d=8, so for example, the C2 code has the root α
, α, α, C1 code may have roots α, α.

Therefore, in the C2 code syndrome calculation, all So=Σri i=0 can be primitive light. Among them, one that can be a generator polynomial for a binary code may be selected as a generator polynomial for a C1 code. In this case, the generating polynomial as the RS code for C1 is G(x) = (x0α) (x+α) and β; if α is considered a new primitive light, G(x) = (x+β) (x1β) It can be seen that this becomes the generating polynomial of the R3 code. Further, a normal R3 code cannot express a generator polynomial using two elements. It should be understood that the above example is a special case that can be expressed using two elements.

Let us explain how to perform C2 decoding using conventional parallel operations.

When correcting one error using So, Ss, 5o=e
i, 5s=ei (α8) The iSO pattern shows an error pattern. Find the error position αi.

, = Ss/So = a81 Therefore, find the error position from i'' (t/s) 10gctx. However, 10gctX is GF (
28) is the logarithm with the base of the primitive light α. Let X be the input pattern and output 10gαX as the output value. The correspondence table is given by logarithmically expressing Table 1. A vector representation is input to the ROM memory as an address pattern, and the contents 10gαX are output.

In Fig. 7, the information input from the information input terminal (1) is
, Ss syndrome calculation circuit + 8]), are respectively calculated by 21 and input to the Galois field division circuit (even) x
= Ss/S.

is executed on the Galois field GF(2). The value X is logarithm RO
It is converted by M and then multiplied by (1/8) by a coefficient unit to become an error order (latched in register 861. On the other hand, the error pattern is latched from register SO to register 861 and accumulated in delay circuit So. The information that was stored is sent to the correction circuit (88
1, and the S4 syndrome recheck circuit checks whether the correction was correct. If correct, the information is output from the output terminal (2), and if an error is detected, the detection information is output from the detection terminal (91). Output.

In the above embodiment, the codes on G F f21 and GF (2) were explained, but the codes on G F f21 and GF (
2m) The above code can also be easily configured. That is, C1 code 0) GF t21 , GF (2”
) Above (7) Raw, FA polynomial wo G + (x),
If G + (x), then G 1(x) = (x +
1) g(X) −・= −(IllG1(x)・(
x+1)(X0αm)...1121g(x) is a primitive polynomial of degree m, and α is the root of g(x).

〔Effect of the invention〕

As described above, since the C1 code can be encoded and decoded as if it were a binary code, the C1 code can be handled in the same way as a binary code while taking advantage of the correction ability of the R8 code. For convenience of explanation, a distance of 3. Although an R3 code with a distance of 14 is used as the C2 code, a combination of R8 codes with any distance is generally possible.

Furthermore, although the explanation has been limited to a two-dimensional code composed of two codes C1 and C2, it is generally applicable to multidimensional codes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional decoding device, FIG. 2 is a block diagram of another conventional decoding device, and FIG. 8 is a block diagram of a conventional CRCC encoding device having a generator polynomial given by equation (1). 4 is a block diagram of a conventional R5 code encoding device having a generator polynomial given by equation (4), and FIG. FIG. 6 is a block diagram of a bit serial encoding device for an original code, and FIG. 7 is a block diagram of an 8-bit parallel encoding device for an R8 code having a generator polynomial of equation (8) according to an embodiment of the present invention is an example of C2 decoding according to the present invention. In the figure, f44) f451 (4η(49) C
an (5's t'a kai) □□□ inversion) (scream (□□□ (6
1 bit register, 146) f481 (2
) i IHn 391 +6 old (g) is 2 modal star, σ
(e) is an 8-bit adder modulo 2, (8D is a syndrome SO calculation circuit, so is an 88 calculation circuit, ■ is a Galois pair division circuit, and (corporate) is a logarithm ROM circuit. Identical or corresponding parts are given the same reference numerals.

Claims (1)

[Claims] 1) C_1 code is binary encoded or Reed/Solo
mon encoding, and the C_2 code is Reed-Solomo coded.
In an encoding/decoding method in which n encoding is transmitted, errors are detected or corrected, and then decoded on the receiving side, the generating polynomial of the C_1 code is transformed into a Galois field of GF(2^m) (m is an appropriate positive integer). By choosing C_1 as the basis of
^+^1, α^i^+^2^l,... C
Roots of _1 code α^j, α^j^+^k, α^j^+^2
An encoding/decoding method characterized in that ^k,... are partially shared. (However, i, j, k, and l are appropriate integers.) 2) The feature is that the generating polynomials of the C_1 code and C_2 code are the following G_1(x), G_1'(x), and G_2(x), respectively. An encoding/decoding method according to claim 1, characterized in that: Generator polynomial of C_1 code G_1(x)=(x^m+1)g(x) However, GF(2
) on G_1'(x)=(x+1)(x+α^m), but on GF(2^m), the generator polynomial of C_2 code G_2(x)=^S_1_1(x+α^j^k), but on GF( j=0 on 2^m) Here, g(x): Primitive polynomial of degree m α: Root S of g(x): An appropriate positive integer, and m=jk.