JPS6146058A - Semiconductor device and reading method thereof - Google Patents

Abstract

PURPOSE:To improve the degree of integration by forming structure in which memory cells in each line arranged along a word line are isolated severally by wells or wells surrounded by insulators at every line. CONSTITUTION:A P type well 21 is shaped onto an insulator 20 while being surrounded by a thick SiO2 film 22. A source and a drain in a MNOST are each formed on both sides of the P well 21 while being brought into contact with the SiO2 film 22, and the source 23 and the drain 24 are shaped by diffusing an N<+> impurity. An extremely thin SiO2 film 25, an Si3N4 film 26 and a gate electrode 27 are formed onto a channel between the source 23 and the drain 24 in order from a lower section. In a memory cell having such constitution, selectivity among word lines can be ensured by back-biassing the well, thus improving the degree of integration as one element/cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device and a reading method therefor, and particularly to a technique that is effective when applied to an EEFROM.

, [Background technology] Programmable non-volatile ROM (Read Onl
yMemory), E P (Erasable
&Program II la-ble) ROM is known. In addition, as a device with further improved integration, EA (E electrically A 1te-
rable) or E E P (E 1ectri
Cally EraSable & Program
mable) ROM is known. For example, M
N OS (Metal N1tride Oxide
Semicon-ductor) type EEPROM
There is something described in the 1982 IEDM Technical Digest, page 733. This EEPROM
has a configuration of two elements per memory cell using a high breakdown voltage MNO8, and enables byte erasing with a striped P-well. FIG. 1 shows a cross section of one memory cell of an EEFROM. In the figure, reference numeral 1 indicates an N-type silicon semiconductor substrate, in which a P-type well 2 is formed. 4 in the P-type well 2 surrounded by a relatively thick 5i02 insulating layer 3;

A switching MOS transistor (hereinafter referred to as MO5T) and an MNOS transistor (hereinafter referred to as MNO3T) are connected in series with each other. That is, among the source 7 and drain 6 formed on both sides below the gate electrode 4 and 5i02 gate oxide film 5 of the MO3T, the source 7 is also the drain 7 of the MN05T. Above the channel to be formed, an extremely thin 5i02 film 9 and an S
An i3N4 film 10 is formed, and a gate electrode 11 of MNOST is formed thereon.

One memory cell of such an EEPROM is connected to each other in a matrix by word lines and data lines, as shown in FIGS. 2 and 3.

That is, the first row memory cells Cl1FCI2...
The gates of MO5T and MNOST of the second row memory cells C21tC22, . .

Furthermore, the memory cells cl, , c2 . ...M
The drains of O3T are interconnected by data line D1, and the second column of memory cells c, 2 . The drains of c22... are interconnected by a data line D2. The sources of MNOST arranged in each column are connected to the potential supply line V
They are interconnected by LI t VL2...

In addition, in such an arrangement of memory cells, the aforementioned P well 2 has memory cells (CttyC21...) t (
CI2 F C2□...) are separated from each other.

In other words, well separation is performed in the data line direction.

By the way, erasing and writing, which are data changes in EEFROM, are performed using the SiO2 film 9 and 5t3 described above.
This is done by trapping electrons and holes in a charge storage area at the interface with the N4 film 1o. For example, while applying a high voltage to P-well 2 for erasing,
The gate of T is grounded and holes are injected into the trap. By writing and erasing in this way, the erased MNOST becomes normally on, and the written MNOST
T can be normally off. Read and write will be explained in more detail with reference to FIGS. 2 and 3.

In the second yA, memory cell C11 is selected as the selection bit.
When reading out data, the word aW1s of the memory cell C11 is multiplied by 5V, for example, and the word aW1s of the word line W1m and the word @ of the non-selected bit memory cell C2I...
W 2 s... and W2m, VL, I, V
L2... Ground the line. Therefore, only MO3T of memory cell C21 of the selected bit is turned on, and M of this bit is turned on.
NOST information can be read on the data line +. In addition,
In this case, only the data line D1 is addressed, and the other data lines D2, . . . are in an open state.

In FIG. 3, when writing data to the memory cell C1+ as a selected bit, a high voltage, for example, 5V is applied to the word line W1g of the memory cell C0, and a high voltage, for example, VP=15V is applied to the word line Wig.

While grounding the other word lines W2s, W2+++... and data line D+, V L + , V L
2...A voltage Vi is applied to the line through resistors R+, R2...

This Vi is approximately 15V, for example. Therefore.

Only MO3T of the memory cell CII of the selected bit is turned on, the channel potential becomes almost Ov, and the M N of this bit is turned on.
A high voltage of 15V is applied to the gate insulating film of the OS T, and the voltage is 1MN.
The threshold voltage of 03T changes and @ can be inserted.

Since the unaddressed data lines D2 are in an open state, the memory cell CI2 is write-inhibited by Vi, and in the worst case, only the threshold voltage is applied to the memory cell C22.

In the conventional EEPROM and its circuit operation described above, the MOST of each memory cell is essential. This is because memory cells are connected in parallel on each data line, so if you do not exclude normally-on memory cells of non-selected bits during reading, the addresses between memory cells on the same data line will be different. This is because the selectivity of the gas is lost. In this way, the conventional E
A and EEPROM require two elements, MOST and MNOST, per memory tl, and EFR
The integration density was lower than that of OM, and it was difficult to improve the integration density.

[Object of the Invention] An object of the present invention is to provide a semiconductor device with an improved degree of integration and a reading method thereof.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention A brief outline of typical inventions disclosed in this application is as follows.

In other words, each row of memory cells arranged along a word line is separated by a well or a well surrounded by an insulator for each row. Can be biased.

Therefore, it is possible to achieve a 1-element/1-bit semiconductor device and a reading method thereof, which can omit the switching MO3) transistor and improve the degree of integration.

[Embodiment 2] Preferred embodiments of the semiconductor device and the reading method of the present invention will be described below with reference to FIGS. 4 to 6.

Figure 4 shows SOI (Silicon On In
1 is a cross-sectional view of one memory cell of a semiconductor device according to the present invention when manufactured using a 5ulator technology. In fig.

Reference numeral 20 is an insulator such as sapphire.

On this insulator 20, a P-type well 21 made of polysilicon or recrystallized polysilicon is formed by being depressed in a thick SiO2 film 22. Here, MI as a memory cell
Among the S elements, the source and drain of 0MN0ST, which is preferably an MNOS transistor (MNOST), are formed on both sides of the P well 21 in contact with 5iOz [22], and the source 23 . The drain 24 is formed by diffusing N+ impurities. On the channel between the source 23 and the drain 24, from the bottom, an extremely thin SiO2 film 25,
A gate electrode 27 is formed of S i3 N4 [26].

As shown in FIGS. 5 and 6, memory cells having such a configuration are connected to each other in a matrix form by data lines and word lines to form a memory array.The feature of the present invention is that the well 21 However, before explaining this, the connection IQ\A of each memory cell will be explained.

5 and 6, the symbols in FIGS. 2 and 3 used to explain the conventional two-element/cell are used again for the sake of brevity for corresponding components. as C, , C12... and C21
9C22... are each memory cell. The gates of MNOST of the memory cells cl, c, 2, .
The gates of the MNOSTs of . . . are each interconnected by a word line W2m. Furthermore, the drains of the MNOSTs of the memory cells C, , C2,... in the first column are interconnected by data 1iAo +, and the drains of the MNOSTs of the memory cells CI'2 v C22... in the second column are interconnected by data 1iAo +. The drains are interconnected by data line D2. Furthermore, the sources of MNOST arranged in each column are interconnected by potential supply lines VL rt , V L 2 , . . . .

In the memory array having such a configuration, the wells 21 described above are separated for each row. Specifically, as shown in FIGS. 5 and 6, the first row of memory cells C,
, , C, 2 . . . are formed with a well W1 indicated by a broken line, and in the second row memory cells C21, C22 . To explain based on the correspondence with FIG. 4, well W1 or well W
2 corresponds to a P-well 21, and this P-well 21 runs in a direction perpendicular to the plane of the paper in the figure. Therefore, the wells 21 in each row are surrounded by the insulator 20 and the 5to2 film 22 and are electrically isolated from each other.

In FIG. 4, the well 21 is formed using SOI technology to facilitate its separation, but the well 21 may be formed directly on the semiconductor substrate as shown in FIG. The wells are separated by a PN junction.

The reason why the semiconductor device of the present invention having the configuration described above can be configured as one element/cell and its degree of integration can be improved will be made clear by explaining its operation.

First, memory cells can be erased in units of wells W+, w2, . . . . That is, while applying a high voltage of, for example, VP=15V to the well W1, the word line W
Memory cell CII erased by grounding 1m
, CI2, . . . can be normally on. In this state, holes are trapped in the charge storage portions of each memory cell CII, C12, . . . . In the case of writing, conversely, electrons may be trapped.

The read operation will be explained with reference to FIG.

For example, when reading data from memory cell C as a selected bit, all word lines are set to ground potential, well W1 corresponding to the selected bit is set to ground potential, well W2 corresponding to non-selected bits, etc.・を－
vBe potential. here.

-Vno is selected to be a back bias potential sufficient to cut off normally-on memory cells among non-selected bits. Therefore, not only normally-off unselected bits but also normally-on unselected bits of memory cells can be cut off by the back bias potential -VSS. Then, the memory cell C of the selected bit
Only data No. 11 is taken into the data line DI. In this way, conventionally a switching MoS transistor was required, but by applying a back bias to the well, unselected bits can be cut off regardless of the information, making a single element/cell configuration possible.

It can also be seen that byte erasing is facilitated by the formation of wells running in the word line direction. Note that during reading, the other data lines D2, which are not addressed, are in an open state, and the potential supply lines VL, VL2, and so on are grounded.

Next, a write operation will be explained with reference to FIG. 6. When writing 8 data into the memory cell C2, for example, all the wells Wl are set as 0 selection bits.

W2... is set to ground potential, potential supply lines vLI, vL2
A voltage Vi is applied to . . . via resistors RI, R2, . This voltage Vi is, for example, a high voltage at the time of erasing vp=
It has a value approximately equal to tsv.

In addition, the word line W1m of the memory cell C11 of the selected bit
Vp=15V is applied to the other non-selected bits, the word line W2rtr... of the other non-selected bits is grounded, and the data line D+ of the selected bit is grounded, and the data line D2 of the non-selected bit is grounded.
... is in an open state. As a result, memory cell C
Only al+ is written, but other non-selected bit memory cells are in a write inhibited state and are not written.

[Effects (1) By separating memory cells in the word line direction from memory cells in other word line directions by a well or a well surrounded by an insulator, the selectivity between word lines is increased by applying a back bias to the wells. Since it is possible to secure
The degree of integration can be improved as one element/cell.

(2) By applying SOI technology, this well formation can be facilitated and the degree of integration can be further improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, an M I S FET having a double structure gate electrode consisting of a floating gate and a control gate is used as a memory element. For example, the present invention is also effective in EPROM, EEPROM, etc.

[Field of Application] The technology of the present invention is effective when applied to non-volatile semiconductor devices such as EPROMs and EEPROMs. The idea of sometimes applying a back bias to this region can be widely applied to other semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a memory cell of an EEPROM with two elements/cell, and FIGS. 2 and 3 are wiring diagrams of a memory array of an EEPROM with two elements/cell. FIG. 4 is a cross-sectional view of a memory cell of a one-element/cell EEPROM according to the present invention, and FIGS. 5 and 6 are a cross-sectional view of a one-element/cell EEPROM according to the present invention.
FIG. 2 is a wiring diagram of a memory array of an EP ROM. 1...N type semiconductor substrate, 2, 21...P well, 3
．． 5,9,22,25...5i02 film, 6,7°23
...Source, 7,8,24...Drain, 4゜11
．． 27...Gate electrode, 10,26...Si3N4
Film, 20... Insulator, Wls, W2s... Word line. Wlm, W2m=・word line, D I + 02'
...Data line, all, c12. c21. c22
-・Memoryse) Lt, V L +. VL2... Potential supply line, Wl j W2... Well.

Claims (1)

[Claims] 1. In a semiconductor device in which memory elements are arranged in a matrix by word lines and data lines, each memory element is composed of one MIS element, and the word lines are arranged in each row. The plurality of MIS elements connected to each word line are connected to the gate electrodes of the MIS elements, the data lines are connected to the drain electrodes of the MIS elements arranged in each column, and the data lines are connected to the drain electrodes of the MIS elements arranged in each column. , are each formed in the same well. 2. The semiconductor device according to claim 1, wherein the well is surrounded by an insulator. 3. Memory elements arranged in a matrix by word lines and data lines are formed by one MIS element, and drain electrodes of the MIS elements arranged in each row are mutually connected to the data lines; A plurality of MIS elements connected to the word line are each formed in the same well, and when reading each memory element, a back bias is applied to the well corresponding to a non-selected bit.
A method for reading a semiconductor device, characterized by cutting off memory elements of non-selected bits.