JPS6145412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to reduce the element accuracy of a companding DA converter having a circuit configuration based on μ=255 companding rule 15-fold line approximation method.

As a companding rule for an analog signal, for example, an audio frequency signal, for an input analog signal X and its full scale value A, the compressed output Y is However, sgn(X) indicates the polarity of the signal X.

It is known that it can be found in the form of , where μ=
255 is called the μ=255 companding rule. There is already a method to obtain a PCM signal by applying encoding processing to the output Y using the μ = 255 companding rule.
It has been commercialized as the PCM-24B system.

Here, when the companding law of μ=255 is approximated by a 15-fold line, the step voltage in the first section, that is, the minimum step voltage is (1/2) ¹² times the full-scale voltage. Therefore, the companding DA converter can be converted into a 12-bit linear DA converter.
When configured with a converter, the accuracy of the element becomes strict, and current technology does not require trimming of the element.
The disadvantage is that it is difficult to implement into LSI.
Another DA conversion method is the counting type DA conversion method. In this case, the element accuracy is converted to time domain accuracy and the passive element accuracy can be reduced, but there is a drawback that the counting clock becomes high and the operating speed of the operational amplifier must be increased.

The purpose of the present invention is to improve element accuracy without trimming.
It is an object of the present invention to provide a companding DA converter that can be reduced to the point where it can be implemented as an LSI, and in which the operating speed of an analog circuit can be set lower than that of a counting type.

In the present invention, a companding DA converter is configured with 6-bit and 8-bit linear DA converters, and it is determined from the input digital signal whether the polarity is positive or negative, and decoding is performed in each of the first to fifth sections. is performed by a 6-bit linear DA converter supplied with an external reference voltage from the 8-bit linear DA converter, and each decoding of the 6th to 8th sections is performed by the 8-bit linear DA converter.

The present invention will be explained in detail below with reference to the drawings.

Figures 1A and B are drawings used in the present invention.
A part of the 15-fold line approximation characteristics of the μ=255 companding rule of the DA converter is shown, or the number of the broken line, that is, the section number is shown, and Δi (i=1 to 8) is the step size of the i-th section. Here, if the minimum step voltage (step voltage in the first section) is 2, then the first
The maximum output value of the section to the 8th section is 31, respectively.
94, 220, 472, 976, 1984, 4000, 8032.
Each step output from the 1st section to the 5th section is
These are obtained by setting the external reference voltages of the 6-bit linear DA converter to 64, 128, 256, 512, and 1024, respectively. These external reference voltages and each step voltage from the sixth section to the eighth section are obtained by applying an external reference voltage having a value of 8192 to an 8-bit linear DA converter.
Therefore, a companding DA converter having the μ=255 companding rule can be constructed from 6-bit and 8-bit linear DA converters.

FIG. 2 shows an embodiment of the circuit configuration of the companding DA converter of the present invention, which is constructed based on the 15-fold line approximation characteristics of the μ=255 companding rule shown in FIGS. 1A and 1B.

In the companding DA converter shown in Fig. 2, 1 is a reference voltage input terminal with positive polarity, 2 is a reference voltage input terminal with negative polarity, 3 is a digital input terminal, 4 is a start pulse input terminal, and 5 is a companding terminal. DA conversion output terminals, 6 and 7 are respectively 6-bit and 8-bit linear DA converters that can be operated by external reference voltages, 8 is a buffer amplifier, 9 and 10 are analog switches, 11 is a clock pulse generator, 12
is a logic control circuit having a successive approximation register that operates at the timing of the clock pulse from the clock pulse generator 11. In operation of this DA converter, digital input is continued from the input terminal 3 to the logic control circuit 12 in response to a start pulse at the input terminal 4. If the polarity sign of the digital input is positive, switch 9 is connected to terminal 1, and if the polarity sign is negative, switch 9 is connected to terminal 2. Next, the logic control circuit 12 decodes the 3-bit section code in the digital input, and if the section code corresponds to one of the first to fifth sections, the switch 10 is switched to the 6-bit linear DA converter 6. The switch 10 is connected to the output terminal of the 8-bit DA converter 7 when the switch 10 corresponds to any of the sixth to eighth sections. Furthermore,
The logic control circuit 12 controls the first to fifth codes for the 4-bit code within the interval during digital input.
In any of the sections, the output of 8-bit linear DA converter 7 is 64, 128, 256, 512, 1024, respectively.
and convert these outputs into a 6-bit linear DA converter 6.
For each of the first to fifth sections, from 2 steps to 32 steps, from 18 steps to 48 steps, and from 26 steps of the steps of the 6-bit linear DA converter 26.
Decode using 56 steps, 30 steps to 60 steps, and 32 steps to 62 steps. However, it is assumed that the least significant bit (LSB) of the digital input of the 6-bit linear DA converter 6 is always set to 1. For the 4-bit code in the 6th to 8th sections, the 8-bit linear DA converter 7
Decrypt directly by

Generally, when the companding rule of μ=255 is approximated by a 15-fold line, the minimum step size _Δ1 is approximately 1/4000 of the full scale, and 12-bit precision is required. However, as explained above, the companding DA conversion of the present invention Since the circuit is configured to satisfy the companding law using 6-bit and 8-bit linear DA converters, there is an advantage that the element precision of these converters can be reduced compared to the case of conventional DA converters. Companding DA of the present invention
The converter is extremely useful for devices that decode telephone audio and for converting the devices into LSI.

[Brief explanation of the drawing]

FIGS. 1A and 1B are characteristic diagrams showing the companding DA converter output-decoding step number characteristic in the case of positive output of the 15-fold line approximation of the μ=255 companding rule used in the present invention,
FIG. 2 is a block diagram showing an example of the circuit configuration of the companding DA converter according to the present invention. 1...Positive reference voltage input terminal, 2...Negative reference voltage input terminal, 3...Digital input terminal, 4...Start pulse input terminal, 5...DA converter output terminal, 6...6
Bit linear DA converter, 7... 8-bit linear DA converter, 8... Buffer amplifier, 9, 10... Analog switch, 11... Clock pulse generator, 12... Logic control circuit.

Claims (1)

[Claims] 1 It has a 15-fold line approximation characteristic of the μ=255 companding rule, a 1-bit polarity sign indicating polarity, and whether the level of the input analog signal is in the first to eighth sections on the positive or negative side of the 15-fold line characteristic. In a companding DA converter that decodes into an analog signal an 8-bit digital signal consisting of a 3-bit interval code specifying whether the data corresponds to the interval and a 4-bit intra-interval code indicating the intra-interval level of the interval, 6-bit linear DA with input terminal supplied with external reference voltage
converter and an 8-bit linear DA converter, and after determining the polarity in the input digital signal, an external reference voltage corresponding to the polarity is applied to the 8-bit linear DA converter.
In addition to the converter, if the interval code in the input analog signal specifies any one of the first to fifth intervals, the analog output from the 8-bit linear DA converter is converted to the 6-bit linear DA converter. It is applied as an external reference voltage to the converter, and the least significant bit of the 6-bit linear DA converter is always set to 1, and the 6-bit linear DA converter outputs an analog output within the range corresponding to the specified section. and when it is determined that the interval is one of the sixth to eighth intervals, the analog output from the 8-bit linear DA converter is extracted to form an analog signal corresponding to the input analog signal. Companding DA converter.