JPS6145367A - Picture processor - Google Patents

Abstract

PURPOSE:To shorten the processing time when the picture data is binary or ter- nary code by using a memory means which stores directly a carry or condition flag delivered from an arithmetic processing part in the form of the binary picture data. CONSTITUTION:No bus controller is provided to a picture memory 8 which stores the binary picture data, and a carry C (1 bit) delivered from an arithmetic logical unit 3 is connected to an input data bus. Then data A and B, for example, of a picture memory 6 are read out at a time and supplied to the unit 3 performs an operation (B-A). The carry C is delivered to the memory 8 to perform the microprogram control to set the write signal under an enable state. Then the carry C is written to the memory 8. Finally the addresses of the memory 8 are increased. These processes are repeated by the number of times equal to the loop frequency. Thus the picture data A are all binary coded.

Description

DETAILED DESCRIPTION OF THE INVENTION G) Technical Field The present invention relates to an image processing apparatus that reduces the time required for FiZ value processing.

(b) Prior Art An image processing device for recognizing the shape and movement of a subject from an image captured by a television camera, for example, has been considered.

A method of binarizing image data is known as one method of image recognition, and FIG. 3 shows the basic configuration of a microprogram type image processing apparatus as an example of a conventional image processing apparatus. In the figure, 1 is a microprogram memory that stores a microprogram consisting of a series of microinstructions;
2 is a sequencer that controls the execution address of the microprogram memory 1 according to the value of carry C, which will be described later; and 3 is an arithmetic logic unit that outputs carry C and control signals. 4
5 is a path controller, 5 is a register that temporarily stores calculation results, 6 is an image memory that stores digital data A of an image taken with a television camera, and 7 is data necessary for binarization processing (for example, a floating threshold value). 8 is an image memory that stores binarized image data Y, 9.10.11.12.13.14 is a bus controller, and 15f′i image memory 6.7.8 address It is an address controller that simultaneously increments . In this device, the addresses of image memories 6, 7, and 8 are all common, and image memory 6 and image memory 7
shall be readable at the same time.

Next, the operation when image data is binarized by the image processing apparatus will be explained with reference to the flowchart of FIG.

First, the address of the image memory 6.7.8 is initialized (F-1). Next, the number of loops is set according to the size of the image memory. For example, if the image data stored in the image memory 6 has a size of 256 dots vertically by 256 dots horizontally, the number of loops is set to the product of 65,536. Note that the number of loops can be controlled within the sequencer 2. Access image memory 6 and image memory 7 simultaneously to read image data A and B. p' -
2) Manually input the arithmetic logic unit 3. The arithmetic logic unit 3 performs the operation (A-B) (F-3). As a result, if A2B, carry C is set to '0', and if A<B, carry C is set to #1' (F-4). Carry Cn Read by the sequencer 2, the destination of the microprogram stored in the microprogram memory 1 is changed depending on the value of carry C. The arithmetic processing up to this point is one cycle of arithmetic theory unit 3, and one
The cycle takes 100-200 μs.

Next, if the carry is “BI,” set 10 (F-5), and if the carry is #0#, set #1’ (F-6) to the arithmetic logic unit 3.
(i.e., loaded from register 5) and output. Then, the output data from the arithmetic logic unit is stored as Y in the image memory 8 (F-7), and the image memory 6
．． 7.8 address 2 CF-8 incremented by address controller 15). Arithmetic processing BI so far
is the next cycle of the arithmetic logic unit 3. The above two cycles are looped for the size of the image memory,
The binarization process is completed.

In this way, two cycles of arithmetic processing are performed for each unit pixel (usually one dot) constituting image data A, and this is repeated for the entire image size, that is, the number of loops (F-
9).

In such an image processing apparatus, there is a problem in that as the number of pixels constituting image data increases, binarization processing takes time, and real-time processing cannot be expected.

(c) Object and structure of the invention The present invention has been made in view of the above points, and aims to provide an image processing device that reduces the time required for binarization processing of image data, and achieves this object. In order to do this, a storage means is provided for storing the carry or condition flag output from the arithmetic processing section as binary image data, and the image data is configured to be read and written in parallel with the arithmetic processing. be.

) implementation column The present invention will be explained below based on the drawings.

FIG. 1 shows an embodiment of an image processing apparatus according to the present invention, in which the same reference numerals as those in FIG. 4 already described indicate the same components. In this embodiment, a carry C (1 bit) output from the arithmetic logic unit 3 is input to the image memory 8 without providing a bus controller for controlling the data bus of the image memory 8 that stores binarized image data. It is connected to a data bus, and the other configuration is almost the same as the conventional column shown in FIG.
Alternatively, it goes without saying that the zero flag may be switched and inputted via the bus controller. Furthermore, if the carry and zero flags are written in the image memory 8 at the same time (for example, the carry is in bit 0 and the zero flag is in bit 1), ternarization of the image becomes possible.

Next, the binarization process according to the present invention will be explained using chart 70 in FIG.

After Yesha rice (p-1), image memory 6°7.
8 and set the number of loops.

Next, data A in image memory 6 and image memory 7.

B is simultaneously read out (P-2) and input to the arithmetic logic unit 3. In Arithmetic 'Jlfq Logical Unit 3 (B-Person)
The calculation is performed (P-3). If A>B, carry C is'
1', if A≦B, the carrier is '0#. Since the carry C is output to the image memory 8, is it the write signal of the image memory 8? Executes micro-four-gram control such as enabling, and writes carry C to image memory 8 (P4
)0 Finally, the address of the image memory is incremented (P-5), and by repeating the process as many times as the loop, the image data Af can be binarized.

In this way, the operation in arithmetic logic unit 3 is (B-
A) is only performed once, and all other controls can be processed in parallel, so the binarization process is completed in one cycle per loop.

In the above embodiment, the carry output from the arithmetic logic unit 3 is directly stored in the image memory, but in addition to the carry, a condition flag such as a zero flag that is set when the operation result is O may be used.

(E) As described in detail, the present invention processes multi-level image data and converts it into binary image data.
53G7 (3) Carry or condition flag output from the arithmetic processing unit in an image processing device? Since we have provided a storage means to directly store it as binary image data,
Binarization processing and ternarization processing of image data are completed in one cycle per loop, so processing time can be shortened without increasing hardware costs, and real-time processing is fully possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the image processing device according to the present invention, FIG. 2 is a flowchart of the binarization processing operation by the device shown in FIG. 1, and FIG. 3 is a block diagram of a conventional image processing device. 4 is a flow chart of the binarization processing operation by the apparatus shown in FIG. 3. 1...Micro program memory, 2...Sequencer, 3...34'4 k control unit, 5...Register 6 glance 7.8...Image memory, 15...Address controller

Claims (1)

[Claims] In an image processing device that performs arithmetic processing on multilevel image data to generate binary image data, a storage means for storing a carry or condition flag output from the arithmetic processing section as binary image data is provided, and the arithmetic processing An image processing device characterized in that it is possible to read and write image data in parallel.