JPS6144872U - Hybrid IC mounting structure - Google Patents

Hybrid IC mounting structure

Info

Publication number
JPS6144872U
JPS6144872U JP13008484U JP13008484U JPS6144872U JP S6144872 U JPS6144872 U JP S6144872U JP 13008484 U JP13008484 U JP 13008484U JP 13008484 U JP13008484 U JP 13008484U JP S6144872 U JPS6144872 U JP S6144872U
Authority
JP
Japan
Prior art keywords
hybrid
mounting structure
terminal
board
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13008484U
Other languages
Japanese (ja)
Inventor
良一 新井
信吾 小島
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP13008484U priority Critical patent/JPS6144872U/en
Publication of JPS6144872U publication Critical patent/JPS6144872U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のハイブリッドＩＣの基板実装方法の斜視
図、第２図は本考案の一実施例の斜視図、第３図は第２
図を上面から見た図、第４図は第２図の側面図である。 １，２，６，７，１１，１２，１５，１６・・・・・・
ハイブリッドＩＣ， ３， ８， １ ７・・・・
・・基板、４・・・・・・ハイブリッドＩＣ１の端子、
５・・・・・・ハイブリッドＩＣ２の端子、９・・・・
・・ハイブリッドＩＣ（，の端子、１０・・・・・・ハ
イブリッドＩＣ７の端子、１３３，Ｂ．〜式２・・・・
・・ハイブリッドＩＣｌ１の端子、１４，Ａ．〜Ａ３。Fig. 1 is a perspective view of a conventional hybrid IC board mounting method, Fig. 2 is a perspective view of an embodiment of the present invention, and Fig. 3 is a perspective view of an embodiment of the present invention.
4 is a side view of FIG. 2; FIG. 4 is a side view of FIG. 2; 1, 2, 6, 7, 11, 12, 15, 16...
Hybrid IC, 3, 8, 1 7...
... Board, 4... Terminal of hybrid IC1,
5...Hybrid IC2 terminal, 9...
...Hybrid IC (terminal of, 10...Terminal of hybrid IC7, 133,B.~Formula 2...
...Hybrid ICl1 terminal, 14,A. ~A3.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ２つ以上のハイブリッドＩＣの基板上での実装において
、一方のハイブリッドＩＣを前記基板を介し他方のハイ
ブリッドＩＣに相対する位置に実装シ、さらに、一方の
ハイブリッドＩＣの端子を、他方のハイブリッドＩＣの
端子の位置から、その端子の並び方についてずらした位
置に実装したことを特徴とするハイブリット’ＩＣの実
装構造。When mounting two or more hybrid ICs on a board, one hybrid IC is mounted at a position opposite to the other hybrid IC via the board, and the terminals of one hybrid IC are connected to the terminals of the other hybrid IC. A hybrid IC mounting structure characterized in that the IC is mounted at a position shifted from the position of the terminal in terms of the arrangement of the terminal.
JP13008484U 1984-08-28 1984-08-28 Hybrid IC mounting structure Pending JPS6144872U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13008484U JPS6144872U (en) 1984-08-28 1984-08-28 Hybrid IC mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13008484U JPS6144872U (en) 1984-08-28 1984-08-28 Hybrid IC mounting structure

Publications (1)

Publication Number Publication Date
JPS6144872U true JPS6144872U (en) 1986-03-25

Family

ID=30688695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13008484U Pending JPS6144872U (en) 1984-08-28 1984-08-28 Hybrid IC mounting structure

Country Status (1)

Country Link
JP (1) JPS6144872U (en)

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