JPS6144429A - Alignment method - Google Patents

Alignment method

Info

Publication number
JPS6144429A
JPS6144429A JP16702084A JP16702084A JPS6144429A JP S6144429 A JPS6144429 A JP S6144429A JP 16702084 A JP16702084 A JP 16702084A JP 16702084 A JP16702084 A JP 16702084A JP S6144429 A JPS6144429 A JP S6144429A
Authority
JP
Japan
Prior art keywords
determined
arrangement
arrangement coordinates
designed
error parameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16702084A
Other versions
JPH0447968B2 (en
Inventor
Toshikazu Umadate
Original Assignee
Nippon Kogaku Kk <Nikon>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Kogaku Kk <Nikon> filed Critical Nippon Kogaku Kk <Nikon>
Priority to JP59167020A priority Critical patent/JPH0447968B2/ja
Publication of JPS6144429A publication Critical patent/JPS6144429A/en
Priority claimed from US06/915,027 external-priority patent/US4780617A/en
Publication of JPH0447968B2 publication Critical patent/JPH0447968B2/ja
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Abstract

PURPOSE: To enable precise alignment with only stepping by calculating corrected arrangement coordinates based on designed arrangement coordinates and an error parameter which is determined with plural actually measured values and actual arrangement coordinates.
CONSTITUTION: A wafer WA is placed on a stage, marks GY, Gθ are detected and the wafer WA is rotated for correction. Then, the positions of the marks SXn, SYn of a specific chip Cn are detected. Then, an error parameter is determined to obtain a minimum mean deviation from an actually measured value and a designed value. Then, the arrangement map of a corrected chip due to a determined error parameter and designed arrangement coordinates is made. Then, the position of the stage is determined by a step and repeat system in accordance with the arrangement map. The above-mentioned method makes the mean error of positioning for all plural chip patterns smaller and enables precise alignment only with stepping.
COPYRIGHT: (C)1986,JPO&Japio
JP59167020A 1984-08-09 1984-08-09 Expired - Fee Related JPH0447968B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59167020A JPH0447968B2 (en) 1984-08-09 1984-08-09

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59167020A JPH0447968B2 (en) 1984-08-09 1984-08-09
US06/915,027 US4780617A (en) 1984-08-09 1986-10-03 Method for successive alignment of chip patterns on a substrate

Publications (2)

Publication Number Publication Date
JPS6144429A true JPS6144429A (en) 1986-03-04
JPH0447968B2 JPH0447968B2 (en) 1992-08-05

Family

ID=15841900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59167020A Expired - Fee Related JPH0447968B2 (en) 1984-08-09 1984-08-09

Country Status (1)

Country Link
JP (1) JPH0447968B2 (en)

Cited By (97)

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JPS63232321A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPS63232326A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPS63232322A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPS63299122A (en) * 1987-05-29 1988-12-06 Canon Inc Aligner
JPH01207604A (en) * 1988-02-15 1989-08-21 Canon Inc Mark position detecting method
JPH01243419A (en) * 1988-03-25 1989-09-28 Hitachi Ltd Position alignment method
JPH0432219A (en) * 1990-05-29 1992-02-04 Canon Inc Alignment method
JPH04271109A (en) * 1991-01-09 1992-09-28 Hitachi Keisokki Service Kk Position alignment method of semiconductor wafer
JPH08330394A (en) * 1996-06-13 1996-12-13 Nikon Corp Alignment method
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Cited By (249)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63232321A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPS63232326A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPS63232322A (en) * 1987-03-20 1988-09-28 Canon Inc Alignment
JPH0468767B2 (en) * 1987-03-20 1992-11-04 Canon Kk
JPH0421332B2 (en) * 1987-03-20 1992-04-09 Canon Kk
JPS63299122A (en) * 1987-05-29 1988-12-06 Canon Inc Aligner
JPH0437574B2 (en) * 1987-05-29 1992-06-19 Canon Kk
JPH01207604A (en) * 1988-02-15 1989-08-21 Canon Inc Mark position detecting method
JPH01243419A (en) * 1988-03-25 1989-09-28 Hitachi Ltd Position alignment method
JPH0432219A (en) * 1990-05-29 1992-02-04 Canon Inc Alignment method
JPH04271109A (en) * 1991-01-09 1992-09-28 Hitachi Keisokki Service Kk Position alignment method of semiconductor wafer
US6002487A (en) * 1995-06-20 1999-12-14 Nikon Corporation Alignment method for performing alignment between shot areas on a wafer
US5792580A (en) * 1995-11-17 1998-08-11 Mitsubishi Denki Kabushiki Kaisha Method of aligning reticle pattern
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US5856054A (en) * 1996-09-03 1999-01-05 Mitsubishi Denki Kabushiki Kaisha Method of alignment in exposure step through array error and shot error determinations
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