JPS6144429A - Alignment method - Google Patents

Abstract

PURPOSE:To enable precise alignment with only stepping by calculating corrected arrangement coordinates based on designed arrangement coordinates and an error parameter which is determined with plural actually measured values and actual arrangement coordinates. CONSTITUTION:A wafer WA is placed on a stage, marks GY, Gtheta are detected and the wafer WA is rotated for correction. Then, the positions of the marks SXn, SYn of a specific chip Cn are detected. Then, an error parameter is determined to obtain a minimum mean deviation from an actually measured value and a designed value. Then, the arrangement map of a corrected chip due to a determined error parameter and designed arrangement coordinates is made. Then, the position of the stage is determined by a step and repeat system in accordance with the arrangement map. The above-mentioned method makes the mean error of positioning for all plural chip patterns smaller and enables precise alignment only with stepping.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an alignment method suitable for a step-and-repeat type exposure apparatus for manufacturing semiconductor devices or an apparatus that performs sequential inspection in a step-and-repeat type, and particularly relates to The present invention relates to a method for precisely aligning a mask or reticle, which is an original plate, and a semiconductor wafer, etc., which is an exposure target.

(Background of the Invention) In recent years, semiconductor devices such as ICs and LSIs have rapidly become finer and more dense, and the equipment that manufactures them, especially the circuit patterns of masks and reticles, has become more and more complex. Exposure devices that superimpose and transfer images are also required to be more precise. It is required that the circuit pattern on the mask and the circuit pattern on the wafer be overlapped with an accuracy of, for example, within 0.1 μm, and for this reason, currently, this type of exposure equipment is capable of overlapping the circuit pattern on the mask with the circuit pattern on the wafer in a local area ( For example, a so-called step-and-repeat system, in which the wafer is exposed a certain distance (for example, for one chip) and then the circuit pattern on the mask is exposed again, is used, especially a reduction projection type exposure device ( Steppers) have become mainstream. In this step-and-repeat method, the wafer is placed on a two-dimensionally moving stage and positioned relative to the projected image of the circuit pattern on the mask, making it possible to precisely overlap the projected image with each chip on the wafer. can. In addition, in the case of a reduction projection exposure system, the alignment marks provided on the mask or reticle and the marks attached to the chips on the wafer are projected and directly observed or detected through a lens for alignment. The alignment method is based on the lens method, and the or-axis method, in which the entire wafer is aligned using a positioning microscope placed a certain distance from the projection lens, and then the wafer is projected and fed under direct pressure. There are two methods: alignment method. Generally, in the through-the-lens method, each chip on the wafer is aligned, so although the overlay accuracy is high, there is a problem that the exposure processing time for one wafer becomes long. In the case of the off-axis method, once the alignment of the entire evaporator is completed, the wafer is simply stepped according to the chip arrangement.
Exposure processing time is shortened. However, since alignment is not performed separately for each chip, satisfactory overlay accuracy cannot always be obtained due to effects such as expansion and contraction of the wafer, rotation error of the wafer on the stage, orthogonality of movement of the stage itself, etc. There wasn't.

(Objective of the Invention) The present invention uses a step-and-repeat alignment method to align all of a plurality of chips arranged on a substrate to be processed such as a wafer with a reference position such as a projection position of a mask pattern. The purpose of the present invention is to provide a method that enables more precise alignment by simply stepping without having to perform any steps.

(Summary of the Invention) The present invention provides a method for placing each of a plurality of chip patterns regularly arranged on a substrate to be processed (a wafer or a seven-dimensional mask) along the designed arrangement coordinates (αβ) at a predetermined reference position (an exposure device In the step-and-repeat method, the designed arrangement of the chip butter is used to sequentially align the pattern projection position of the mask or reticle, or the inspection field of view or inspection position of the inspection probe needle in the case of an inspection device. Coordinate value (D
xn.

(Step 103
, 104, 105, 106) and the actual array coordinate values (Fxn) that should not be aligned with the designed array coordinate values and the step-and-repeat method.

Fyn ) includes predetermined error parameters (transformation matrix A including residual rotation θ of the wafer, orthogonality W of the stage, linear expansion and contraction R of the wafer, and matrix O of the offset amount of the two-dimensional position of the wafer). Unique relationship (determinant Fn=A-D
n+O), multiple actual measured values (Fxn
, Fyn) and the actual array coordinate values (Fxn, F
yn ), the step of determining the error parameters (A, O) (step 107), and the process of determining the determined error parameters (A, O) and the design so that the average deviation (address error E) is minimized. The upper array coordinate value (Dxn + Dyn
), the actual array coordinate value (Fxn) is obtained from the above unique relational expression.

Step 108) of positioning the substrate to be processed according to the calculated actual array coordinate values (Fxn, Fyn) during step-and-repeat positioning (steps 109, 110.1)
12).

(Embodiment) FIG. 1 is a perspective view showing a schematic configuration of a reduction projection exposure apparatus suitable for carrying out the method of the present invention. The reticle R serving as a projection original is positioned so that its projection center passes through the optical axis of the projection lens 10, and is mounted on the apparatus. The projection lens l displays the circuit pattern/image drawn on the reticle R.
15, or "/10"' and projected onto the wafer WA.

The wafer holder 2 vacuum-chucks the wafer WA and is provided so as to be minutely rotatable with respect to a stage 3 that moves two-dimensionally in the X direction and the X direction. A drive motor 4 is fixed on the stage 3 and rotates the ueno holder 2. Further, movement of the stage 3 in the X direction is performed by driving a motor 5, and movement in the X direction is performed by driving a motor 6. A reflecting mirror 7 with a reflecting plane extending in the X direction and a reflecting mirror 8 with a reflecting plane extending in the X direction are fixedly installed on two orthogonal sides of the stage 3, respectively. A laser beam interferometer (hereinafter simply referred to as a laser interferometer) 9 projects a laser beam onto a reflecting mirror 8 to detect the position (or amount of movement) of the stage 3 in the X direction, and a laser interferometer 10 detects the position (or amount of movement) of the stage 3 in the A laser beam is projected onto the mirror 7 to detect the position (or amount of movement) of the stage 3 in the X direction. An off-axis wafer alignment microscope (hereinafter referred to as WAM) 20.21 is installed on the side of the projection lens 1 in order to detect (or observe) Ueno/WAJ alignment marks. It is being Note that in FIG. 1 of the WAM 21fl, it is located after the projection/zoom 1 and is not shown. WAM20.21 each has an optical axis parallel to the optical axis AX of projection/z1,
A strip-shaped laser spot light ysp extending in the X direction,
θSP is imaged onto the wafer W. (spot light YSP
is not shown in Figure 1. ) These spot lights YSP,
θSP is light of a wavelength that does not sensitize the photosensitizer (photoresist) on the wafer WA, and in this embodiment, it vibrates minutely and fluently in the X direction. The WAMs 20 and 21 have a photoelectric element that receives scattered light and diffracted light from the mark, and a circuit that synchronously rectifies the photoelectric signal with the vibration period of the spot light, and the vibration of the spot light θ5P (YSP) in the X direction. The amount of deviation of the mark in the X direction from the center (outputs an alignment signal according to the amount of deviation of the mark in the X direction).

Therefore, the WAM20.21 has a configuration equivalent to a so-called spot light vibration scanning type photoelectron microscope.

Now, this apparatus is provided with a laser step alignment (hereinafter referred to as LSA) optical system for detecting the mark of the Ueno W ball through the projection lens 1. A laser beam LB generated from a laser light source (not shown) and passed through an ex-bang, silica/trical lens, etc. (not shown) has a wavelength that does not expose the photoresist, and enters the beam splitter 30 to be split into two. It is divided into two beams. One of the laser beams is reflected by the mirror 31, passes through the beam splitter 32, and is converged by the imaging lens group 33 so that the cross section becomes a strip-shaped spot beam, and then the reticle R and the projection lens 1 The light enters the first folding mirror 34, which is arranged between the two and so as not to block the projection optical path of the circuit pattern. The first folding mirror 34 reflects the laser beam upward toward the reticle R. The laser beam is provided below the reticle R and is incident on a mirror 35 having a reflection plane parallel to the surface of the reticle R, where it is projected and reflected toward the center of the beam 1 near the incidence. mirror 35
The laser beam from
The image is formed as YS. Spot light Lysi wafer WA
It is used to detect the position of a diffraction grating mark extending in the X direction by relatively scanning it in the X direction. When the spot light LYS illuminates the mark, diffracted light is generated from the mark. The optical information is projected again and returns to the beam splitter 3, the mirror 35, the mirror 34, the beam splitter group 33, and the beam splitter 34.
4 and enters an optical element 36 consisting of a condenser lens and a spatial filter.

This optical element 36 transmits diffracted light (first-order diffracted light and second-order diffracted light) from the mark, blocks specularly reflected light (zero missing light), and receives the diffracted light via a mirror 37 at a photoelectric element 38. Focuses light on a surface. The photoelectric element 38H outputs a photoelectric signal according to the amount of diffracted light collected. As described above, the mirror 31, the beam splinter 32, the imaging lens group 33, the mirror 34 .
35, optical element 36, mirror 37, and photoelectric element 38V
i. Through-the-lens alignment optical system (hereinafter referred to as Y-L) that detects the position of the mark on the wafer W in the X direction.
(referred to as an SN system).

On the other hand, another laser beam split by the beam splinter 30 is transmitted to a through-the-laser alignment optical system (hereinafter referred to as
- I'C is input (referred to as LSA system). Just like the X-LSASA system and the Y-LSA system, it is composed of a mirror 41, a beam splinter 42, an imaging lens group 43, a mirror 44, 45, an optical element 46, a mirror 47, and a photoelectric element 48. A strip-shaped spot light LXS elongated in the X direction is imaged.

The main controller 50 receives the photoelectric signal from the photoelectric element 38.48, the 7 time signal from the WAM 20.21, and the laser interferometer 9. The position information from lO is input, and one calculation process is performed for alignment, and the motors 4,
Outputs the command for driving 5.6. This main control device 50 is equipped with an arithmetic processing section such as a microcomputer or a minicomputer.
Design position information (such as chip arrangement coordinate values on the wafer WA) of a plurality of chips CP formed on the WA is stored.

Figure 2 shows the above WAM20, 21, Y-I, SA system, X-
Spot light θSP, YSP by LSA system.

LYS, LXS projection/imaging plane (wafer WA
FIG.

In FIG. 2, when a coordinate system xy is defined with the optical axis AX as the origin, the y-axis and the y-axis each represent the moving direction of the stage 3. In FIG. 2, the circular area centered on the optical axis AX is the image field if, and the rectangular area inside it is the projected image Pr of the effective pattern/area of the reticle R. The spot light LYS is formed at a position outside the projection image Pr within the image field if and coincident with the X-axis, and the spot light LXS is also formed at a position outside the projection image Pr within the image field if and aligned with the X-axis. Formed to match the top. On the other hand, two spotlights θSr, YSF
A line segment (parallel to the y-axis) that is a distance Yo from the vibration center Tdx axis in the X direction! The traps are set so as to coincide with the above, and the distance Dx in the X direction is set to a value smaller than the diameter of the wafer WA. In this device, the spot light θSP,
YSP is arranged symmetrically with respect to the y-axis, and the main controller 50 controls the spot light θS with respect to the projection point of the optical axis AX.
It stores information regarding the positions of P and YSP. The main controller 50 also stores information regarding the center position of the spot light LYS in the X direction (distance XI) and the center position of the spotlight LXS in the X direction (distance Yl) with respect to the projection point of the optical axis AX.

Next, the alignment method according to the present invention using this device will be explained with reference to the operation of the device and the chart 70 in FIG. Note that this alignment is performed for the second and subsequent layers of the wafer WA, and chips and alignment marks have already been formed on the wafer WA.

First, in the wafer WAH step 100, a linear notch (
7 rats) are roughly positioned so that they face in a certain direction. The flat of the wafer WA is y as shown in FIG.
positioned parallel to the axis. Next step 1
At step 01, the wafer is transferred onto the wafer holder 2 of the WAH stage 3, and seven rats are placed on the wafer holder 2 so as to remain parallel to the y-axis, and vacuum suction is carried out. The wafer W
For example, AI'C includes multiple steps Cn as shown in FIG.
are formed in a matrix along orthogonal arrangement coordinates αβ on the wafer WA. The α axis of the array coordinate αβ is approximately parallel to the 7 rats of the wafer WA. In FIG. 4, among the plurality of chips Cn, the wafer WA with the array coordinates αβ is representative.
Chips C0 to C lined up in a row on the α axis passing through almost the center of
It only represents 6. Each of the chips Co to C6 is provided with four alignment marks GY, Gθ, sx, and sy. Now, when the center of chip C3 in the center of chips Co to C6 is taken as the origin of the array coordinate αβ,
On the α axis, there is a diffraction grating mark S extending linearly in the α direction.
Y0 to SY are provided in the right brain of chip Co-C, respectively. Also, on the β axis passing through the center of the chip C3, there is a mark SX3 in the shape of a diffraction grating extending linearly in the β direction.
3 and the other chip COr Cl + C
21C4.

c5. The same goes for C6Vc - mark 5Xo-8X2, SX4 to SX on the line passing through the center of the chip and parallel to the β axis
6 is provided. These marks SYn and 5XnU are detected by spot lights LYS and LXS, respectively. Also, below each chip 00-C6 are marks GYo-GY6. which are used to align the entire wafer WA (global alignment). Gθ. ~
Gθ6 is provided. These marks GYn, Gθn
is formed of a diffraction grating pattern extending linearly in the α direction on a line segment parallel to the α axis. Among the steps C and -C, which are roughly arranged in a line in the α direction, for example, the leftmost step C
The distance in the α direction between the mark GYo of No. 8 and the mark Gθ6 of the right-most chip C6 is determined to match the distance DX between the spot lights θsp and ysp of M20.21 to W. In other words, in this embodiment, marks G are placed at two separate locations.
Y.

wafer WA using the or-axis method using mark Gθ6.
Perform global alignment. Therefore, the other marks GYY~GY6 and mark Gθ.

~Gθ5V1 is originally unnecessary and may be omitted. The point is that two marks extending long and thin in the α direction on a line segment parallel to (or coinciding with) the α axis of the wafer WA need only be present at a distance DX.

Now, the main controller 50 determines the position information of the stage 3 when receiving and taking the wafer WA from the pre-alignment device, and the marks GYo and Gθ from that position. are respectively WAM21.
Stage 3 until the position is within the detection (observation) field of view of 20
Information such as the direction of movement and amount of movement is stored in advance as constants specific to the device. Therefore, in the next step 102,
The main controller 50ti first drives the motors 5 and 6 to position the stage 3 so that the mark GY is located within the detection field of view of the W-input M21. After that, spot light YS
The main controller 50 precisely positions the stage 3 in the X direction based on the alignment signal from the WAM 21 and the position information from the laser interferometer 9 so that the vibration center of P coincides with the center of the mark GYO in the X direction. do. Spot light Y
When the vibration center of SP and the center of mark GYo match,
While the main controller 50V′i motor 6 is under servo (feedback) control using the alignment signal from the WAM 21 to maintain this state, the mark Gθ6 is set to the WAM 2.
The motor 4 is driven to rotate the wafer holder 2 so as to be detected by the zero spot light θSP. Furthermore, the WAM2
The motor 4 is servo controlled by the alignment signal from 0. Through the above series of operations, the spot light YSP and the mark GYo match, the spot light θSP and the mark Gθ6 match, and the rotation of the array coordinate αβ of the wafer W with respect to the moving coordinate system of the stage 3, that is, the coordinate system xy. The deviation is corrected, and the correspondence (regulation) regarding the position r1tVc in the X direction (β direction) of the coordinate system xy and the array coordinate αβ is completed. Next, chip C3 located at the center of wafer WAJ:
The mark SX is the X-LSA type spotlight LXSIC.
Therefore, after positioning the stage 3 so as to be scanned, it is moved in the X direction. At this time, the position of the wafer WA in the X direction when the mark SX3 coincides with the spot light LXS is determined based on the time-series photoelectric signals from the photoelectric element 48 of the main controller 50 and the position information from the laser interferometer 10. Detect and store. This completes the correspondence between the coordinate system xy and the array coordinate αβ regarding the position in the X direction (α direction). Note that this correspondence in the X direction is unnecessary if the X-LSA system is used immediately before the exposure operation. Through the above operations, the global alignment of the wafer WA (corresponding to the coordinate system xy of the array coordinates αβ), which is mainly an off-axis type alignment, is completed. Then, using the conventional method, we used the array design value (array coordinate α) of each chip on the wafer WA.
Based on Ic (center coordinate value of the chip at After positioning (attrage), the chip is exposed (printed).

However, by the time the global alignment is completed, the accuracy of the alignment detection system, the setting accuracy of each spot light, and the optical and geometrical state of each mark on the wafer WA (7
Errors occur due to fluctuations in position detection accuracy due to the effects of 0 process, etc., and the chips on the wafer WA are not always precisely aligned (addressed) in accordance with the xy coordinate system. Therefore, in the embodiment of the present invention, the error (hereinafter referred to as shot address error) is assumed to be caused by the following four factors.

(1) Rotation of the wafer: This occurs because, for example, when correcting the rotation of the wafer WA, the positional relationship between the two spot lights YSP and θSP, which serve as the reference for alignment, is not accurate.6D, coordinate system x
It is expressed as the residual rotational error amount θ of the array coordinate αβ with respect to yVc.

(2) Orthogonality of the coordinate system xy; This occurs because the feeding directions of the motor 5.6 of the stage 3 are not exactly orthogonal, and is expressed by the orthogonality error amount W.

(3) Linear expansion and contraction of the wafer in the X (α) direction and the y (β) direction;
is to expand and contract as a whole. For this reason, the actual chip position deviates by a minute amount in the α and I directions with respect to the designed arrangement coordinate values of the chip, which is particularly noticeable in the peripheral area of the wafer WA. The amount of expansion and contraction of the entire wafer is RX and R3/ in the α(X) direction and β(y) direction, respectively.
It is expressed as However, Rx is the X direction (α
The ratio of the measured value and the designed value of the distance between two points in the X direction (β direction) on the wafer WA, Ry is expressed as the ratio of the measured value and the designed value of the distance between the two points in the X direction (β direction) on the wafer WA. Therefore, Rx, Ry
When both are Vcl, there is no expansion or contraction.

(4) Offset in the X (α) direction and the y (β) direction; this is due to the detection accuracy of the alignment system, the positioning accuracy of the wafer holder 2, etc.
This is caused by a slight deviation in the direction, and is expressed by offset amounts ox and oy.

Now, in FIG. 4, the remaining rotation error amount θ of the wafer WA and the orthogonality error amount W of the stage 3 are exaggerated.

In this case, the orthogonal coordinate system xy actually becomes an oblique coordinate system x y/K tilted by a minute amount W, and the wafer WA is rotated by θ with respect to the orthogonal coordinate system xy.

When the above error factors (1) to (4) are added, the shot position (FXn, Fyn) that should actually be positioned for the shot (chip) at the design coordinate position (D x n r DY n ) is as follows: It is expressed as However, n is an integer and represents a shot (chip) number.

Here, W is originally an infinitesimal amount, and θ is also pushed to an infinitesimal amount by global alignment, so by performing −th order approximation, O is expressed by equation (1) V′i equation (2) This equation (2) Therefore, the positional deviation (εxt1, εyn) from the design value at each shot position is 0 expressed by equation (3).Now, when equation (2) is rearranged into the matrix calculation formula 1ciF, it becomes as follows.

Fn = ON・Dn + O・”(4) However, when the actual shot position (chip position is measured by mark detection and the actual measurement value is detected as Fn, the positional deviation from the shot position Fn to be positioned is , that is, the address error En(Fn-Fn) is minimized. Input the error parameter (transformation matrix), 0 (offset) so that
Determine. Therefore, if the least squares error is taken as the evaluation function, the address error EVi is expressed by equation (9).

(9) Therefore, the error parameters A and 0 are determined so as to minimize the address error E.

However, in equation (9), m represents the number of chips (shots) actually measured among the plurality of chips on the wafer WA.

Now, if the least squares method is used to obtain the error parameters A and O, the amount of calculation is large in this '1 case, so the error parameters 0 (Ox, Oy) are determined separately in advance. Offsect i (Ox, Oy
Since this is the global offset value of the YTd wafer WA, it is best to use a value that averages the address error with respect to the design value (Dxn, Dyn) over several meters of the actually measured chip position Fn on the wafer WAO Ox= □ ...αQ By the way, the shot position Fn to be positioned and the actual measurement value 1
The component Exn in the X direction of the error En between
~(8), Exn = Fxn −Fxn = Fxn −all
Dxn-a12Dyn-Qx...
α3, and the component Eyn of the error En in the X direction is similarly Ey
n = Fyn - Fyn = Fyn - a21 D
xn −a22Dyn OY −(13) Therefore, if the error parameter 8 is determined so as to minimize the error E in equation (9), the element all l JL
121a211a22 is as follows.

II II
II6c6Cd Once the element a11 r al2 r a21 + a22 is determined, the linear expansion/contraction amount RX, R)l, the residual rotation error amount θ, and the orthogonality error amount W are immediately determined from equation (6).

RX = al 1-(i81 RY = az2"49 θ = a2x/RY, = a21/a22
-anW"-(azx/R)') (a12/Rx
) = (1121/a2g) (axz/a1x)
・In order to determine the error parameter input, 0, it is necessary to
-Marks SXn and SY using LSA system and Y-LSA system
n: Actual measurement of position (Fxn, Fyn)
In addition to finding the actual measured chip design value (Dxn.

Dyn) using the formula α(1, Ql), (14)~
It is sufficient to perform the calculation in (17).

Therefore, the explanation of the operation will be continued by returning to the flowchart shown in FIG. After the global alignment is completed, the main controller 50 measures the positions of the plurality of chips on the wafer W4. First, in step 103, the main controller 50iX-LSA
The spot light LXS of the system is located at the leftmost chip coV in Figure 4.
After positioning the stage 3 based on the array design values so that it is lined up parallel to the mark S X o attached to the mark S X .

The stage 3 is moved (scanned) by a certain amount in the X direction so that it crosses the spot light LXS. During this movement, the main controller 50 stores the time-series photoelectric signal waveform of the photoelectric element 48 in association with the position information in the X direction from the laser interferometer 10, and from the waveform state, marks SXo and spot light LXS
The position X□ at the time when the

Next, the main control unit [50 is a step 104 in which the Y-LSA spot light LYS is attached to the mark SYo attached to the chip co.
The stage 3 is positioned based on the array design values so that it is aligned parallel to the stage 3. After that 5, mark SY0 is spot light L
The stage 3 is moved by a certain amount in the X direction so as to cross the YS. At this time, the main controller 50 stores the waveform of the time-series photoelectric signal of the photoelectric element 38 in association with the position information in the X direction from the laser interferometer 9, and from the waveform state marks SY.
The position yo at which point o and the spot light LYS coincide in the X direction is detected. Then, in step 105, the main controller 50 determines whether or not similar position detection has been performed for m chips, and if not, proceeds to Stella 7'106, and moves to another chip on the sea urchin ISW with the array design value. The stage 3 is moved based on , and the same position detection operation is repeated again from step 103. In this embodiment, for example, as shown in FIG.
+ C6+ C7r C13 and center chip C3, total 5
It is assumed that the position detection in steps 103 and 104 is performed for each of the two chips. Therefore step 10
When it is determined that m=5 in 5, the main controller 50 has 5.
This means that two actual measured values (Fxn, F)'n) are stored. That is, (Fxl+F)'2) thousand (Xo+)'o) - chip C0
(FXz, FY2)=(Xa,)'3)-chip C3(
"51 shares) = (Xa,)'a)...Chip C6 (FX
++Fy4)=(x7+y7)・"Chip C'y(F"
s, F)'5) = (xa, ys)...Step C8 5
Two actual measured values are detected sequentially. When detecting these five measured values, if the measured value of a certain chip is significantly different from the design value (Dxn, Dyn)K of that chip, for example, the positioning accuracy determined by clobal alignment is twice as high. If the values are different from each other, the actual measurement value for that chip may be ignored and, for example, the actual measurement of the mark position may be performed for a chip adjacent to that chip.

This is because if the mark on the nap you are trying to measure happens to be deformed during the processing process, or if there is dust attached to the mark, the contrast of the optical image of the mark (
This is to compensate for the deterioration in accuracy of position measurement that occurs when the generated intensity of the diffracted light is weak and the S/N ratio of the photoelectric signal is low.

In addition, as a method to compensate for the deterioration in the accuracy of position measurement, the positions of six or more chips, for example, the chips located in each of the four quadrants of array coordinates αβ in FIG. The design value (Dxn) of each chip is selected from the nine actual measured values in the measurement section.

Dyn) K A method of selecting five actual measured values in order of closestness,
Alternatively, there is a method of simply not using measured values (Fxn, Fyn) that are significantly different from design values (Dxn, Dyn) in subsequent arithmetic processing.

'eK, the main controller 50 in step 107 performs the previous two α1. The error parameter 8,0 is determined based on αυ and the formula α-an. In making this determination, the main controller 50 selects in advance five design values for each chip that has detected the five actual measurement values, and the design values (Dxn, Dy
n) is stored as follows.

(DXI ID)'1) = (Xo'+)'o')"'Chip C0 (D x2 + D Y 2n = (x3', y
3'n...Chip C3 (Dxi+DYs) = (xa'
+y6')"・Chip C6 (DX4 ID)'4)=(
X7', Yt')...f7pC7(Dxs + D
Y 5)"(x13Z y e') "・Chip C8 Also, prior to determining the actual error parameters A and O, each position of the five chips is measured (so-called step alignment)
For example, while moving stage 3 in step 106 in FIG.
~ < 171 can be executed at the same time (7 can be performed. In other words, the algebraic sum of the data (actual value, design value) for each chip in the formula (11, aυ, Q4) ~ The calculation elements shown are sequentially added each time the actual measurement (step alignment) of one chip is completed.The calculation elements are as follows.

In the example, 'rim=5) Furthermore, among these calculation elements, if the chip to be measured on the wafer WA is determined in advance and there is no change, 13
It is also possible to calculate before executing steps 103, 104, 105, and 106 in the figure. If some calculations are performed in parallel with the actual measurement operation in this way, the overall alignment time will not be so long. Then, at the stage when the five actual measured values are obtained, the main control unit et50 uses the results of the above calculation elements to calculate the offset amount (Ox, Oy) using the formula no, aυ, and then calculates the offset value and the above calculation element. Using the result of , further formula (14) −(
171, array element a11 + alz l a31
+ a22 is calculated.

Through the above calculation operations, the error parameters A and 0 are determined, so in the next step 108 of the main controller 50V, the position to be positioned for each chip of the wafer WN is determined using the equation (4), that is, the error parameter The corrected shot address (Fxn, Fxy) is calculated, and the design value (D x n
A chip arrangement map (shot address table) corrected for +D Y n ) is created. For example, for chip co, this array map is the position (FXo, F).
'o), position (Fxl, Fyx) for chip C1
,..., etc., each position data is stored corresponding to the chip number. Next, the main controller 50V1 sets step 109 in FIG. Stage 3 is positioned using the step-and-repeat method (attrage blowfish). As a result, the chips of the queries 15WA, . If the exposure of all the chips on the sea urchin ISW is not completed in step 111, step 111 is performed again.
Repeat the step-and-repeat operation from 9 onwards.

If it is determined in this step 111 that the exposure of all chips on the UniNo WA has been completed, the wafer WA is anoroded in the next step 112, and the entire exposure process for one wafer is completed.

As mentioned above, as is clear from the embodiments of the present invention, the wafer W
Tip for stamp alignment on A.

As the number increases, the measurement accuracy improves, but the measurement time increases accordingly. Therefore, from the viewpoint of reducing measurement time and improving measurement accuracy, it is desirable to select five chips for step alignment as shown in FIG. However, if the minimum line width of the circuit patterns to be overlaidly exposed is not so thin (for example, 2 to 5 μm) and there is no need to improve measurement accuracy, Ueno-W
Three chips apart from each other on A (e.g. co1c6+
It is sufficient to perform stamp alignment (measurement of the position of the chip) for (, y), and the measurement time is considerably shortened.

Also, during step alignment, the X direction of each chip,
Marks SXn attached to multiple chips that perform step alignment, rather than detecting the positions in both the and X directions.
are scanned relative to each other at once using the X-LSA system's spotlight LXS (stage scanner is used to detect only the position of each chip in the X direction, and then each mark SYn of each chip is scanned by the Y-LSA system's spotlight It is also possible to detect the position of each chip in the X direction by performing relative scanning at once using the spot light LYS.In this way, there are multiple chips to be measured in the same column or row of the chip arrangement. When it exists, faster position measurement can be expected than when position detection is performed in both the VcX direction and the X direction for each individual chip.

In addition, if the main controller 50 inputs data from a keyboard device (not shown) to arbitrarily select which chip on the wafer WA is to be stamp aligned/aligned, data can be changed depending on the processing conditions of the wafer WA. It is possible to respond more flexibly to the surface condition (especially the shape of the mark), and it is expected that the accuracy of position measurement will improve. It's a box, a shikikan.
In determining the offset amount (Ox, Oy) using the offset, for example, only the position measurement results of chips within a specified range from the center of the wafer WA may be used. For example, the specified range is set within a circle with a diameter half the diameter of the wafer WA), and the size of the range is determined by the exposure device (reduced/
It is advisable to arbitrarily vary it according to the accuracy characteristics of the projector (projection type, same-magnification projection, proximity stepper, etc.).

Furthermore, in this embodiment, the formula (
4) was applied to perform beat-type attrition blowing on the stenopur/de.However, the surface of the wafer W is divided into several regions (blocks), and the optimal alignment is performed for each block. Equation (4) can be applied in exactly the same way to so-called block alignment. For example, in FIG. 5, the four chips Co located in each quadrant of the array coordinates αβ;
C3゜After performing step alignment for a total of nine chips, C6, C7, and CB, and detecting the actual measured value of the position of each chip, 2Qf) for each quadrant of the array coordinate αβ)
, (11), Q4) ~ (error using lη) Parameter A.

0 and further use equation (4) to determine the position (Fxn.

For example, for the block in the first quadrant with array coordinates αβ, use the actual measured values of one chip in the first quadrant and the four chips C3 + C6r C7. Determine equation (4), and for the block in the second quadrant, one chip in the second quadrant and the chip CO
Equation (4) is determined using the measured values of the four chips r C3+C7. During actual exposure, the shot position (Fx
n, Fyn), the chips on the wafer WA are aligned with the projected image Pr. In this way, position detection and alignment defects due to nonlinear elements on the wafer are reduced, and unlike conventional block alignment,
Since the housing blocks can be formed while leaving the averaging elements, there is an advantage that the overlay accuracy within each block is approximately averaged for all chips. In addition, great advantages can be obtained when the present invention is used in combination with an exposure apparatus other than a stepper, especially a mirror projection exposure apparatus. Generally, the chip array of a wafer printed with a mirror projection exposure apparatus is often curved. Therefore, when overlapping exposure is performed on the wafer using a stepper (mixed use; mix
If block alignment is performed as described above, the curvature of the chip arrangement within each block becomes negligibly small, making it possible to perform printing with extremely high overlay accuracy over the entire wafer surface.

As described above, an exposure apparatus suitable for the embodiment of the present invention is used to irradiate a mark on a wafer WA with a laser spot light,
Although the position of the mark (chip) has been detected, an alignment system that makes the spot light vibrate in simple harmonic motion on the wafer WA or performs uniform linear scanning, or the mark on the reticle R and the mark on the wafer WA can be It can be carried out in exactly the same way with an exposure apparatus using a so-called Gui-Pai di-alignment optical system in which alignment is performed by observing (detecting) through a microscope objective lens placed above the microscope. In this case, Gui
If the reticle R is not slightly moved in the x and y directions for positioning during bi-die alignment, the projected image of the mark on the reticle R will be the same as the spot light LXS of this embodiment.
, it becomes a trap that corresponds to LYSIC. Also reticle R&
In the fine movement type, first, the reticle R is set to accurately match the origin position. When stamp aligning (actual measurement) multiple chips, after stamping the stage according to the array design values, move the reticle so that the mark on the reticle R and the mark on the chip to be measured are in a predetermined positional relationship. Slightly move R to adjust x, y from the origin of reticle R.
By detecting the amount of movement in the direction, it is possible to calculate the actual measured value of the position of the tip (r eyebrows 1 71).

In addition, in this embodiment, the offset amount (Ox, Oy) is determined based on the lateral pressure alone to simplify the calculation process.
It goes without saying that the error parameter 0 that minimizes the address error E in equation (9) may be calculated by strict arithmetic processing.

(Effects of the Invention) As described above, according to the method according to the present invention, 9.1 exposed substrates with small alignment errors on average for all of the plurality of chip patterns on the target substrates such as wafers can be used. The number of non-defective chips that can be obtained from this process increases, and the productivity of semiconductor devices can be improved. In addition, since the positions of several chips with respect to the substrate to be exposed are actually measured (step alignment), that is, position measurements using marks of the same shape are repeated multiple times, so the mechanical
There is also the advantage that electrical random errors are reduced. In addition, statistical processing suppresses variations in the sensitivity of the alignment sensor (microscope) for position detection, improving overall alignment accuracy.

Furthermore, according to the embodiment, since the least squares method is used to determine the error parameters, it is possible to suppress variations in accuracy of steng alignment/alignment for several chips. The present invention is not limited to reduction projection type exposure apparatuses, but can be widely applied to step-and-repeat type exposure apparatuses, such as life-size projection type steppers and gloximity type steppers (X-ray exposure apparatuses). be.

In addition to exposure equipment, equipment (defect inspection, propper, etc.) that inspects semiconductor wafers and photomasks with multiple chip patterns, etc., uses a step-and-repeat method for each chip to adjust the inspection field of view and the reference position of a glove needle, etc. The present invention can be implemented in the same manner even in the case where the positioning is performed using the same method.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for an embodiment of the present invention, and FIG. 2 is a plan view showing the positional relationship of each detection center of the alignment system in the apparatus shown in FIG. , FIG. 3 is a 70-chart diagram representing the overall operating procedure using the alignment method of the present invention, and FIG. 4 is a wafer suitable for alignment and exposure using the apparatus of FIG. 1. FIG. 5 is a plan view of the wafer showing the positions of chips to be stamp aligned. [fL term of the sign of the main 4p dimensions] WA...to the sea urchin, CP, Cn...to the oak 1°αβ...
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No 109 No 10. III'...The first two chapters of the disaster; Nazu 7 sequence of disasters: The 9th anniversary of the disaster.

Claims (1)

[Claims] In a method of sequentially aligning each of a plurality of chip patterns regularly arranged on a substrate to be processed along designed arrangement coordinates with respect to a predetermined reference position by a step-and-repeat method, Prior to alignment, the step of moving the substrate to be processed based on the designed arrangement coordinate values of the chip patterns and actually measuring each position when some of the plurality of chip patterns are aligned with the reference position. and; When it is assumed that the designed array coordinate values and the actual array coordinate values to be aligned by the step-and-repeat method have a unique relationship including a predetermined error parameter, the plurality of actual measured values determining the error parameter so that an average deviation between the actual array coordinate value and the actual array coordinate value is minimized; An alignment method comprising the steps of: calculating coordinate values, and positioning the substrate to be processed according to the calculated actual array coordinate values during step-and-repeat alignment.