JP2011029458A - Method and apparatus for manufacturing multilayer semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem caused when laminating a plurality of semiconductor chips on a wafer, wherein processing time for positioning is extremely lengthened, thereby damaging productivity. <P>SOLUTION: A method of manufacturing a multilayer semiconductor device includes an acquisition step of respectively acquiring observed coordinate values for a plurality of indices prepared on a semiconductor substrate in which a plurality of circuit regions are formed, a calculation step (S102) for calculating an error parameter such that a difference between converted coordinate values obtained by converting designed coordinate values for the plurality of indices held in advance by a coordinate conversion formula specified by a predetermined error parameter, and the observed coordinates for the plurality of indices acquired by the acquisition step, is minimized, and an arrangement step (S103) for determining the arrangement positions of a plurality of semiconductor chips fragmented corresponding to circuit regions respectively by the designed coordinate values and the coordinate conversion formula and arranging them in each of the plurality of circuit regions on the semiconductor substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a stacked semiconductor element, and an apparatus for manufacturing a stacked semiconductor element.

  One technique for improving the effective mounting density of semiconductor devices is a structure in which a plurality of semiconductor chips are stacked. In the stacked semiconductor module having a structure in which semiconductor chips before packaging are stacked, the mounting density is improved and the wiring between the semiconductor chips is shortened, so that the processing speed is also improved. In addition, by stacking semiconductor chips having different manufacturing processes, a function that cannot be formed by a single type of semiconductor chip can be provided.

  In the manufacturing process of the stacked semiconductor module, it takes time to cure the adhesive in the joining process. For this reason, rather than stacking and bonding semiconductor chips and semiconductor chips, a procedure for further separating the semiconductor chips after stacking and bonding to a wafer, which is a semiconductor substrate, or a procedure for separating after stacking and bonding two wafers Is more productive. Patent Document 1 below describes, as an example of the latter, a method for manufacturing a semiconductor element in which a semiconductor element is separated after bonding a wafer on which a plurality of semiconductor elements are formed and an interposer.

JP 2003-1000094 A

  However, the difference between the design value and the actual value at the wafer level in the manufacturing process (hereinafter referred to as an error) becomes a size that cannot be ignored compared to the error at the chip level. The error at the wafer level may be, for example, due to wafer expansion and distortion, due to exposure deviation by the exposure apparatus, or due to processing of each of the wafers to be overlapped by different apparatuses. Therefore, when semiconductor chips or wafers are superimposed on the coordinates as designed, even if the alignment is successful in one circuit area, the other circuit area may be completely displaced.

  Thus, when stacking semiconductor chips on a wafer, the process of stacking the semiconductor chip index and the corresponding circuit area index on the wafer after observing the position with a microscope is confirmed for each semiconductor chip. It was repeated. When a plurality of semiconductor chips are stacked on a wafer in this way, the processing time for alignment has become remarkably long, which hinders productivity.

  In order to solve the above-described problem, a first aspect of the present invention is a method for manufacturing a stacked semiconductor device, in which measured coordinate values of a plurality of indexes provided on a semiconductor substrate on which a plurality of circuit regions are formed. Each of the acquisition step, the design coordinate values of a plurality of indices stored in advance, converted coordinate values converted by a coordinate conversion formula defined by a predetermined error parameter, and the plurality of indices acquired by the acquisition step The calculation step for calculating the error parameter so that the difference from the actual measurement coordinate is minimized, and the arrangement positions of the plurality of semiconductor chips separated into pieces corresponding to the circuit area by design coordinate values and coordinate conversion formulas, respectively. Determining and disposing each of the plurality of circuit regions on the semiconductor substrate.

  According to the second aspect of the present invention, there is provided a manufacturing apparatus for a stacked semiconductor device, which obtains measured coordinate values of a plurality of indices provided on a semiconductor substrate on which a plurality of circuit regions are formed, respectively. The difference between the converted coordinate value obtained by converting the design coordinate values of a plurality of indices and a plurality of indices held in advance by a coordinate conversion formula defined by a predetermined error parameter, and the measured coordinates of the plurality of indices acquired by the acquisition section And a calculation unit for calculating an error parameter, and a plurality of semiconductor chips separated into pieces corresponding to a circuit area, by determining the arrangement position by design coordinate value and coordinate conversion formula, respectively, a semiconductor substrate And an arrangement portion arranged in each of the plurality of circuit regions.

  The above summary of the invention does not enumerate all necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a perspective view showing the concept which arrange | positions a semiconductor chip on a wafer. It is a schematic block diagram of the aligner 200. It is explanatory drawing for calculating | requiring a coordinate transformation type | formula. It is a flowchart explaining the process until a laminated semiconductor element is manufactured. It is a perspective view showing the other concept which arrange | positions a semiconductor chip on a wafer.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a perspective view showing a concept of arranging semiconductor chips on a wafer. A plurality of circuit regions 111 are formed in a wafer 101 which is a semiconductor substrate. As shown in the drawing, a plurality of circuit regions 111 surrounded by a rectangle are widely arranged two-dimensionally on the upper surface of the wafer 101. And the design coordinate value regarding the arrangement position of each circuit area | region 111 on the wafer 101 is managed separately.

  A plurality of alignment marks are provided on the wafer 101 together with the circuit region 111. The alignment mark is an index provided outside the circuit region 111 and used for position control of the wafer 101. For each alignment mark, for example, design coordinate values are individually managed as coordinate values with the center of the wafer 101 as the origin. In the figure, three alignment marks 121, 122, 123 are shown as an example, but the number is not limited to three. Although the number may be increased according to the required alignment accuracy, it is preferably less than the number of circuit regions 111 from a practical viewpoint. The relationship between the number of alignment marks and the alignment accuracy will be described later.

  The plurality of semiconductor chips 131 are manufactured by dividing a circuit area formed in the same manner as the wafer 101 by dicing. Each of the separated semiconductor chips 131 is stacked on the circuit region 111 of the wafer 101 in a one-to-one relationship. Therefore, a circuit corresponding to the circuit in the circuit region 111 is formed on the lower surface of the semiconductor chip 131 that is a surface facing the circuit region 111.

  At the same time, a chip index used as a handling reference is provided on the lower surface of the semiconductor chip 131 and is used when the chip is placed on the wafer 101. This chip index may be provided separately irrespective of the function of the circuit, or a characteristic structure in the circuit, for example, the tip of a TSV (Through Si Via) that is a through electrode may be used as the chip index. good. The specific usage of the chip index will be described later.

  The semiconductor chip 131 is preferably thinned by grinding the upper surface, which is a surface where no circuit is provided, by CMP or the like. For example, while the thickness of the wafer is about 600 μm, the thickness can be reduced to less than 100 μm by grinding. By stacking the semiconductor chips that have been ground and thinned in this way, it is possible to increase the mounting density per unit volume of the stacked semiconductor element that is a finished product. Furthermore, the mounting density can be increased more effectively by increasing the number of semiconductor chips to be stacked to two, three,...

  Next, an apparatus for placing the semiconductor chip 131 on the circuit region 111 of the wafer 101 and its operation will be described. FIG. 2 is a schematic configuration diagram of the aligner 200. The aligner 200 functions as an apparatus for manufacturing a stacked semiconductor element.

  The wafer mounting XY table 201 moves in the xy direction shown in the drawing with respect to the base 203 provided on the gantry. The movement of the wafer mounting XY table 201 is realized by driving motors provided in the x and y directions under the control of the control unit 230. The wafer 101 described with reference to FIG. 1 is placed on the upper surface of the wafer placement XY table 201. The mounted wafer 101 is sucked and held by a negative pressure suction mechanism provided on the wafer mounting XY table 201. Thereby, the wafer 101 can be moved to an arbitrary position on the order of microns. Note that the negative pressure suction mechanism provided in the wafer mounting XY table 201 is switch-controlled between the suction state and the non-suction state by the control unit 230.

  Similarly to the wafer mounting XY table 201, the semiconductor chip mounting XY table 202 moves in the xy direction with respect to the base 203 provided on the gantry. The movement of the semiconductor chip mounting XY table 202 is realized by driving motors provided in the x and y directions under the control of the control unit 230. A plurality of semiconductor chips 131 described with reference to FIG. 1 are placed on the upper surface of the XY table 202 for placing semiconductor chips. The mounted semiconductor chip 131 is sucked and held by a negative pressure suction mechanism provided in the semiconductor chip mounting XY table 202. Thereby, the mounted semiconductor chip 131 can be moved to an arbitrary position on the order of microns. The negative pressure suction mechanism provided in the semiconductor chip placement XY table 202 switches the suction state and the non-suction state individually for the plurality of semiconductor chips 131 placed by the control unit 230. Can be controlled.

  The semiconductor chip 131 placed on the semiconductor chip placement XY table 202 is individually moved by the handler 220 to a predetermined circuit area 111 of the wafer 101 placed on the wafer placement XY table 201. The handler 220 is configured to include an arm 221, a fine adjustment unit 222, and a suction unit 223. The arm 221 rotates around the z axis, and the suction unit 223 can be moved above the wafer mounting XY table 201 and above the semiconductor chip mounting XY table 202. The suction unit 223 sucks and holds the individual semiconductor chips 131 to be moved. The fine adjustment unit 222 can be slightly displaced in the rotation direction around the x direction, the y direction, and the z axis in a state where the suction unit 223 holds the semiconductor chip 131 by suction.

  Further, the fine adjustment unit 222 advances and retreats by a small amount in the z direction, and cooperates with the suction unit 223 to suck the semiconductor chip 131 above the semiconductor chip placement XY table 202 and above the wafer placement XY table 201. The suction is released, and the semiconductor chip 131 is placed in a predetermined circuit region 111 of the wafer 101. The semiconductor chip 131 placed in the circuit region 111 is temporarily fixed to the wafer 101 with an adhesive or the like. The temporary fixing is performed by the semiconductor chip 131 being moved in the z direction by the fine adjustment unit 222 in the z direction. This is realized by slightly pressurizing the region 111. Therefore, once the semiconductor chip 131 is temporarily fixed to the circuit region 111, the wafer 101 can be carried out to another apparatus in an overlapped state, that is, in a stacked state.

  The operation of each component of the handler 220 is controlled by the control unit 230. The control unit 230 controls the operation of each component of the entire aligner 200 as described above, not limited to the operation of each component of the handler 220. Therefore, for example, at the timing when the suction unit 223 sucks the semiconductor chip 131 on the semiconductor chip placement XY table 202, the suction mechanism of the semiconductor chip placement XY table 202 turns off the suction of the semiconductor chip 131. The cooperative action of The wafer 101 and the plurality of semiconductor chips 131 are loaded into the aligner 200, and the wafer 101 on which the plurality of semiconductor chips 131 are stacked is unloaded from the aligner 200 using a robot arm. The control unit 230 also exchanges control signals and the like regarding the operation of the external device.

  A wafer microscope 211 equipped with an image sensor is fixed to the casing ceiling of the aligner 200 so that the wafer 101 can be observed from above the wafer mounting XY table 201. In particular, the positions of the alignment marks 121, 122, and 123 are observed here. Specifically, for example, when acquiring the position information of the alignment mark 121, the control unit 230 moves the wafer mounting XY table 201 in the x direction and the y direction so that the alignment mark 121 comes to the center of the image acquired by the image sensor. Move in the direction. And the actual measurement coordinate value as an actual position of the alignment mark 121 is acquired with the movement amount. Similarly, the measured coordinate values are obtained for the other alignment marks.

  The design coordinates of the circuit area 111 that are individually managed using a coordinate conversion formula derived from the actual coordinate values of the plurality of alignment marks acquired in this way and the design coordinate values determined at the time of design. The semiconductor chip 131 is arranged by correcting the value. A specific coordinate conversion formula and application of correction will be described later.

  A semiconductor chip microscope 212 provided with an image sensor is fixed between the wafer mounting XY table 201 and the semiconductor chip mounting XY table 202 so that the semiconductor chip 131 held by the suction unit 223 can be observed from below. Has been. In particular, the position of the chip index is observed here. Specifically, the control unit 230 moves the arm 221 and the fine adjustment unit 222 so that the chip index comes to the center of the image acquired by the image sensor. Using the position of the handler 220 in this state as a reference, the amount of movement of the corrected circuit area 111 to the design coordinate value is calculated, and the semiconductor chip 131 is moved and arranged on the circuit area 111.

Next, application of the coordinate conversion formula and correction will be described. FIG. 3 is an explanatory diagram for obtaining a coordinate conversion formula. The difference between the design coordinate value of the alignment mark on the wafer 101 and the circuit area 111 and the actual measurement coordinate value, which is an actual value, is due to the expansion and distortion of the wafer and due to the exposure deviation by the exposure apparatus. As mentioned. This error is approximately expressed by a rotation amount θ due to rotation of the wafer 101 and an offset amount (x ₀ , y ₀ ) due to an offset in the x and y directions as main error parameters. Hereinafter, an example in which these are used as error parameters will be described.

ただし、ｎ＝１，２，３
…（１） The design coordinate values of the alignment marks 121, 122, and 123 are ( _xd1 , _yd1 ), ( _xd2 , _yd2 ), and ( _xd3 , _yd3 ), respectively. In addition, the actually measured coordinate values are (x _r1 , y _r1 ), (x _r2 , y _r2 ), and (x _r3 , y _r3 ), respectively. Also, the coordinate values obtained by converting the design coordinate values by the coordinate conversion formula using the rotation amount θ and the offset amount (x ₀ , y ₀ ) are respectively (x _c1 , y _c1 ), (x _c2 , y _c2 ), (x _c3 , _yc3 ). At this time, the coordinate conversion formula is expressed by formula (1).

However, n = 1, 2, 3
... (1)

…（２）
具体的には、最小二乗法などの公知の手法により算出されるので、詳細については省略する。 The error parameters θ and (x ₀ , y ₀ ) are obtained by using the measured coordinate values and assuming that the residual sum of squares expressed by the following equation (2) is minimized.

... (2)
Specifically, since it is calculated by a known method such as a least square method, the details are omitted.

When θ and (x ₀ , y ₀ ), which are error parameters, are determined in this way, the coordinate conversion formula (1) is determined. Then, if this coordinate conversion formula is applied to the design coordinate value of the circuit area 111, the coordinate value close to it can be corrected as the design coordinate value without obtaining the actual measurement coordinate value of each circuit area 111. It can be obtained by calculation. Therefore, the control unit 230 converts the semiconductor chip 131 adsorbed by the adsorption unit 223 into a coordinate value obtained by applying the coordinate conversion formula without observing the circuit region 111 to be arranged with the wafer microscope 211. You can take it directly. In this way, all the semiconductor chips 131 are stacked and arranged on the circuit regions 111 to be targeted.

…（３） The error parameter is not limited to the rotation amount θ due to the rotation of the wafer 101 and the offset amount (x ₀ , y ₀ ) due to the offset in the x direction and the y direction. If it is desired to correct the error more precisely, the error parameter may be increased. For example, a coordinate conversion equation can be constructed by applying error parameters such as an orthogonality error in the coordinate system and linear expansion and contraction in the x and y directions of the wafer. The coordinate system is actually an oblique coordinate system in which one axis is rotated by a small angular rotation amount ω, and when the expansion / contraction magnification in the x direction is R _x and the expansion / contraction magnification in the y direction is R _y , coordinate conversion is performed. The equation is expressed by equation (3).

... (3)

  However, in this case, since the error parameters increase, in order to determine these, it is necessary to increase the number of alignment marks to be actually measured. That is, when the error parameter is increased, it can be said that the number of alignment marks needs to be increased accordingly.

  Next, the flow from the state where the wafer 101 is placed on the wafer placement XY table 201 and the semiconductor chip 131 is placed on the semiconductor chip placement XY table 202 to the manufacture of the stacked semiconductor element is shown. explain. FIG. 4 is a flowchart illustrating a series of processing.

  In step S <b> 101, the control unit 230 acquires the alignment marks 121, 122, and 123 on the wafer 101 placed on the wafer placement XY table 201 using the wafer microscope 211 and acquires the wafer placement XY table 201. Observe movement in conjunction. Thereby, the actually measured coordinate values of the alignment marks 121, 122, 123 are acquired. The acquired actual measurement coordinate value is stored in a storage unit included in the control unit 230.

  In step S102, the calculation unit included in the control unit 230 reads the acquired actual measurement coordinate value and the design coordinate value previously managed in the storage unit from the storage unit, and follows the procedure described with reference to FIG. Is calculated. When the error parameter is calculated, the coordinate conversion formula is determined, and is stored in the storage unit.

  In step S <b> 103, the control unit 230 drives the handler 220 and picks up the semiconductor chip 131 from the semiconductor chip mounting XY table 202. At this time, the control unit 230 may move the semiconductor chip mounting XY table 202 as necessary so that the handler 220 can easily pick up the target semiconductor chip 131. Then, the control unit 230 drives the handler 220 so that the picked-up semiconductor chip 131 comes to the vicinity of the optical axis above the semiconductor chip microscope 212. Then, the semiconductor chip microscope 212 is in a state in which the position of the chip index of the semiconductor chip 131 adsorbed by the adsorption unit 223 can be observed. The control unit 230 coordinates the acquired image obtained by the semiconductor chip microscope 212 with the movement of the arm 221 and the fine adjustment unit 222 so that the chip index becomes the center of the acquired image. Then, the calculation unit of the control unit 230 obtains the corrected design coordinate value of the circuit region 111 on which the currently attracted semiconductor chip 131 is to be stacked using the coordinate conversion formula determined in step S102. As a result, a path having the current chip index position as the start point and the corrected design coordinate value as the end point is determined. Therefore, the control unit 230 drives the handler 220 according to this path, and the semiconductor chip 131 is moved to the circuit area 111. To place. Then, the semiconductor chip 131 is temporarily fixed by driving the fine adjustment unit 222 in the direction of the wafer 101 and slightly applying pressure. The operation in step S103 is repeated for the number of semiconductor chips 131 to be arranged.

  In step S103, a plurality of semiconductor chips 131 are temporarily fixed on the wafer 101. In step S104, the control unit 230 cooperates with an external control unit to carry out from the aligner 200 using a robot arm. To do. The wafer 101 unloaded from the aligner 200 is loaded into a bonding apparatus and is heated under pressure to securely bond the semiconductor chip 131 to the wafer 101.

  The wafer 101 to which the semiconductor chip 131 is bonded is carried into a dicer in step S105, and the wafer 101 is diced along the bonded semiconductor chip 131. By this series of processes, a stacked semiconductor element is manufactured.

  In the above description, the processing steps are described in which the semiconductor chip 131 is temporarily fixed to the wafer 101 and is unloaded from the aligner 200 and loaded into the bonding apparatus. However, in the temporary fixing step of Step S103, by changing conditions such as the adhesive layer, temperature, and pressure, it is possible to replace the temporary fixing and bonding as the main step instead of temporary fixing. In that case, the joining process of step S104 is omitted.

  In the above description, the configuration in which one semiconductor chip 131 is stacked in each circuit region 111 of the wafer 101 has been described. However, the number of semiconductor chips 131 to be stacked is not limited to one. In order to further increase the mounting density, it is required to increase the number of layers, such as three layers, four layers,..., So the process of step S103 is repeated, and another semiconductor chip 131 is further placed on the arranged semiconductor chip 131. May be stacked.

  As described above, the arrangement position of the semiconductor chips 131 to be stacked on the wafer 101 can be determined by calculation without observing the individual circuit regions 111 of the wafer 101, so that the processing time for alignment is greatly reduced. And productivity can be improved.

  Next, a modification of the above embodiment will be described with reference to FIG. FIG. 5 is a perspective view showing another concept of arranging semiconductor chips on a wafer. In the above-described embodiment, the alignment marks 121, 122, and 123 provided outside the circuit region 111 are used as a plurality of indexes on the wafer 101. In the modification, a circuit index 512 provided in the circuit area 511 of the wafer 501 is used.

  The circuit index 512 is provided in the circuit area 511, but it is not necessary to be provided separately regardless of the circuit, and a circuit component that can be used as an index may be used as the circuit index. For example, in a stacked semiconductor element, a TSV (Through Si Via) that is a through electrode is often used for connection between layers, but the tip of the TSV can also be observed by the wafer microscope 211, and this is used as a circuit index. be able to.

  There are circuit indicators 512 in the circuit area 511, respectively. Instead of observing all of these, the actual coordinate values are obtained, but the circuit indicators 512 corresponding to the number determined according to the number of error parameters are selected. Then, using it as a selection index, the actual coordinate value of only the selection index is obtained. In the above-described embodiment, the measured coordinate values of the three selection indexes 521, 522, and 523 are obtained here in the same manner as the measured coordinate values of the three alignment marks 121, 122, and 123 are acquired.

  As in the above-described embodiment, the selection indices 521, 522, and 523 on the wafer 501 placed on the wafer placement XY table 201 are used to acquire an image by the wafer microscope 211 and move the wafer placement XY table 201. Observe them in cooperation. Thereby, the actually measured coordinate values of the selection indexes 521, 522, and 523 are acquired. Alternatively, since the semiconductor chip 131 is also arranged in the circuit region 511 where the selection indexes 521, 522, and 523 are present, both the entire circuit region 511 and the semiconductor chip 131 are observed for these three as in the conventional technique. Then, the semiconductor chip 131 is actually temporarily fixed while aligning, and the actual measurement coordinate value is acquired from the result. If the actual measurement coordinate value can be acquired in this way, the coordinate conversion formula can be determined in the same manner as described above. Therefore, the remaining semiconductor chips 131 can be arranged without actually observing the circuit area 511, so that the processing time for alignment can be greatly shortened.

  In addition, the plurality of indexes on the wafer 101 may be provided on a scribe line through which a cutter or the like passes when the wafer is separated into semiconductor chips. Further, when the circuit area is provided inside the circuit area, the circuit area may be an LSI area.

  Next, further modifications will be described. In the above embodiment, after the semiconductor chip 131 is temporarily fixed in step S103, the wafer 101 is unloaded from the aligner 200 in step S104, and the process proceeds to the bonding process. However, another wafer can be stacked on the plurality of temporarily fixed semiconductor chips 131. That is, a plurality of separated semiconductor chips 131 are stacked so as to be sandwiched between two wafers. The wafer and the semiconductor chip thus laminated can be easily heated under pressure in the bonding apparatus, and a laminated semiconductor element having a higher mounting density can be manufactured.

  Specifically, since the individual semiconductor chips 131 are arranged at the design coordinate values corrected using the coordinate transformation formula determined in step S102 (step S103), the actual measurement coordinates of the alignment marks of the wafers to be further stacked are arranged. The wafers are stacked so that the residual sum of squares with the value is minimized. The wafers to be stacked are transferred downward by a transfer robot different from the handler 220. Further, for wafers that are transported downward, the measurement coordinate value of the alignment mark may be obtained by sharing the semiconductor chip microscope 212 in the transport path, or of course, may be obtained in advance by another apparatus.

  Thereafter, similarly to the above-described embodiment, the control unit 230 cooperates with an external control unit, and is carried out from the aligner 200 using a robot arm and carried into the joining apparatus. The two wafers and the plurality of semiconductor chips 131 sandwiched between them are pressed and heated by a bonding apparatus to be integrated. After being integrated and laminated, the semiconductor device is diced with a dicer to produce a laminated semiconductor element having a higher mounting density.

  In the example described above, an example in which another wafer is stacked on the plurality of semiconductor chips 131 temporarily fixed to the wafer 101 is shown. However, instead of this, the wafer 101 and the plurality of semiconductor chips 131 are heated. After integration by pressure, another wafer can be stacked on the plurality of semiconductor chips 131.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

101 wafer, 111 circuit area, 121, 122, 123 alignment mark, 131 semiconductor chip, 200 aligner, 201 wafer mounting XY table, 202 semiconductor chip mounting XY table, 203 base, 211 wafer microscope, 212 semiconductor chip Microscope, 220 handler, 221 arm, 222 fine tuning unit, 223 suction unit, 230 control unit, 501 wafer, 511 circuit area, 512 circuit index, 521, 522, 523 selection index

Claims (8)

An acquisition step for acquiring measured coordinate values of a plurality of indices provided on a semiconductor substrate on which a plurality of circuit regions are formed, and
The difference between the converted coordinate value obtained by converting the design coordinate values of the plurality of indexes held in advance by a coordinate conversion formula defined by a predetermined error parameter, and the measured coordinates of the plurality of indexes acquired by the acquisition step A calculation step for calculating the error parameter so that is minimized,
The plurality of semiconductor chips separated into pieces corresponding to the plurality of circuit areas are respectively arranged by the design coordinate values and the coordinate conversion formulas, and are arranged in each of the plurality of circuit areas on the semiconductor substrate. A method for manufacturing a stacked semiconductor element, comprising an arranging step of arranging.   The method for manufacturing a stacked semiconductor device according to claim 1, wherein the plurality of indices are alignment marks provided on the semiconductor substrate and outside the plurality of circuit regions.   2. The method for manufacturing a stacked semiconductor device according to claim 1, wherein the plurality of indices are indices selected from indices provided inside the plurality of circuit regions. The obtaining step obtains the measured coordinate values when individually observing and arranging the number of the selected index among the singulated semiconductor chips on the selected index,
The method of manufacturing a stacked semiconductor device according to claim 3, wherein in the placing step, individual semiconductor chips other than the semiconductor chips placed by obtaining the measured coordinate values are placed on the semiconductor substrate.   The method for manufacturing a stacked semiconductor device according to claim 3, wherein a through electrode is used as an index provided inside each of the plurality of circuit regions.   6. The stacked semiconductor device according to claim 1, further comprising a stacking step of stacking another semiconductor substrate different from the semiconductor substrate on the plurality of semiconductor chips disposed by the placing step. 6. Manufacturing method.   In the stacking step, the difference between the placement position of the plurality of semiconductor chips arranged and the measured coordinate values of the plurality of indices provided on the other semiconductor substrate corresponding thereto is minimized. The method for manufacturing a stacked semiconductor device according to claim 6, wherein another semiconductor substrate is overlaid on the plurality of semiconductor chips. An acquisition unit for acquiring measured coordinate values of a plurality of indices provided on a semiconductor substrate on which a plurality of circuit regions are formed;
The difference between the converted coordinate value obtained by converting the design coordinate values of the plurality of indexes held in advance by a coordinate conversion formula defined by a predetermined error parameter, and the measured coordinates of the plurality of indexes acquired by the acquisition unit A calculation unit for calculating the error parameter so that is minimized,
The plurality of semiconductor chips separated into pieces corresponding to the plurality of circuit areas are respectively arranged by the design coordinate values and the coordinate conversion formulas, and are arranged in each of the plurality of circuit areas on the semiconductor substrate. An apparatus for manufacturing a stacked semiconductor element, including an arrangement portion to be arranged.

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