JPH0447968B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an alignment method and apparatus suitable for a step-and-repeat type exposure apparatus for manufacturing semiconductor devices or an apparatus for performing sequential inspection in a step-and-repeat type. In particular, the present invention relates to a method and apparatus for precisely aligning a mask or reticle, which is an exposure original, and a semiconductor wafer, etc., which is an exposure target.

(Background of the Invention) In recent years, semiconductor devices such as ICs and LSIs have rapidly become smaller and more densely packed. Exposure equipment that superimposes and transfers images is also required to be more precise. It is required that the circuit pattern on the mask and the circuit pattern on the wafer be overlapped with an accuracy of, for example, within 0.1 μm.For this reason, currently, this type of exposure equipment overlaps the circuit pattern on the mask in a local area (for example, one chip) on the wafer. The so-called step-and-repeat system uses a so-called step-and-repeat system, which repeats the process of exposing the wafer by a certain distance (stepping) and exposing the circuit pattern on the mask again.
In particular, reduction projection type exposure apparatuses (steppers) have become mainstream. In this step-and-repeat method, the wafer is placed on a two-dimensionally moving stage and positioned relative to the projected image of the circuit pattern on the mask, making it possible to precisely overlap the projected image with each chip on the wafer. can. In addition, in the case of a reduction projection exposure system, a through-the-lens lens that directly observes or detects the alignment marks provided on the mask or reticle and the marks attached to the chips on the wafer through a projection lens and aligns them. Off-axis alignment method, in which the entire wafer is aligned using an alignment microscope placed a certain distance from the projection lens, and then the wafer is sent directly under the projection lens. There are two methods. Generally, in the through-the-lens method, each chip on the wafer is aligned, so although the overlay accuracy is improved, there is a problem in that the exposure processing time for one wafer is increased. In the case of the off-axis method, once the alignment of the entire wafer is completed, the wafer is simply stepped according to the chip arrangement.
Exposure processing time is shortened. However, since positioning is not performed for each chip, satisfactory overlay accuracy may not always be obtained due to the effects of expansion and contraction of the wafer, rotation error of the wafer on the stage, orthogonality of movement of the stage itself, etc. Nakatsuta.

(Object of the Invention) The present invention uses step-and-repeat alignment to align all of a plurality of chips arranged on a substrate to be processed, such as a wafer, with a reference position such as a projected position of a mask pattern. It is an object of the present invention to provide a method that enables more precise alignment simply by stepping without having to do so.

(Summary of the Invention) The first aspect of the present invention is to form a plurality of chip patterns regularly arranged on a substrate to be processed (wafer or photomask) along the designed arrangement coordinates αβ.
In a step-and-repeat method, a chip is Pattern design array coordinates
A step of moving the substrate to be processed based on Dxn and Dyn and actually measuring each position (,) when some of the plurality of chip patterns are aligned with the reference position (steps 103, 104, 105, 106);
The designed array coordinate values and the actual array coordinate values (Fxn, Fyn) to be aligned using the step-and-repeat method are determined by predetermined error parameters (wafer residual rotation θ, stage orthogonality W, wafer linear expansion/contraction). When it is assumed that there is a unique relationship (determinant Fn=A・Dn+O) including the transformation matrix A containing R and the matrix O of the offset amount of the two-dimensional position of the wafer, a plurality of actual measured values ( , ) and the actual array coordinate values (Fxn, Fyn), the first calculation step (step 107) of determining the error parameters A, O so that the average deviation (address error E) is minimized, and the determination error parameter A,
A second calculation step (step 108) of calculating the actual array coordinate values (Fxn, Fyn) from the above unique relational expression based on O and the designed array coordinate values Dxn, Dyn, a step-and-repeat method The technical point is that the process includes a step (steps 109, 110, 112) of positioning the substrate to be processed according to the calculated actual array coordinate values (Fxn, Fyn) during alignment.

Furthermore, the second and third inventions of the present application are based on the above-mentioned first invention.
The present invention relates to an apparatus that uses the method of the invention to align a substrate to be processed, such as exposure, or a substrate to be inspected, to be inspected.

In other words, multiple areas to be processed or areas to be inspected
A substrate WA in which Cn is regularly formed in two dimensions,
a stage 3 that holds the processing area so that its array coordinates (α, β) are substantially parallel to a predetermined orthogonal coordinate system (x, y) and moves two-dimensionally within the orthogonal coordinate system; , position measuring means 9 and 10 for measuring the coordinate position of the stage, and a processing center point or an inspection center point at a predetermined position within the orthogonal coordinate system.
AX, processing means for processing a region Cn of the substrate on the stage or inspection means R, 1 for inspecting the region Cn, and one of the specific points set inside each of the plurality of regions is the processing means for processing the region Cn of the substrate on the stage. control means 5, 6, 50 for controlling the movement of the stage so that it is guided to a predetermined positional relationship with respect to the center point or the inspection center point;
The present invention relates to an alignment device comprising: Further, in the second and third inventions, (a) the designed arrangement coordinates (α, β) of the plurality of regions Cn;
(b) storage means for storing design coordinate values Dn of the stage 3 that lead each specific point of the plurality of regions Cn to the processing center point or the inspection center point AX based on; (b) among the plurality of regions Cn; Each specific point in m areas is processed by actually measuring the coordinate position of each specific point in m (m<n) areas that are different from each other based on the measurement values of the position measuring means 9 and 10. Actual measurement means 30 to 38, 41 to 48, 50, 103, 10 for specifying the coordinate values of the stage 3 to match the center point or the inspection center point AX
(c) Stage 3 for aligning each specific point of the plurality of areas Cn with the processing center point or inspection center point AX;
In order to calculate the movement coordinate value Fn of , based on the design coordinate value Dn, predetermined error parameters A, O
a first calculating means 108 that calculates Fn=A・Dn+O using; (d) each actual measured coordinate value of the m regions and each design coordinate value Dn corresponding to each of the m regions; , a second calculation means 107 is provided for calculating values of error parameters A and O that minimize the deviation between each measured coordinate value and the moving coordinate value Fn in each of the m or less actually measured regions. The control means 5, 6, 50 calculate the first calculation means 1 using the calculated error parameters A and O.
Stage 3 is set to the movement coordinate value Fn determined in 08.
are moved sequentially.

A fourth invention of the present application relates to a positioning device for exposing a pattern area such as a reticle to overlap each shot area on a photosensitive substrate.

That is, a plurality of shot areas Cn arranged two-dimensionally according to predetermined array coordinates (α, β)
and accompanying each of the plurality of shot areas,
A sensitive substrate WA on which marks SXn and SYn are formed, which are arranged in a fixed positional relationship with the center point of each shot area, is arranged in a predetermined orthogonal coordinate system x,
a stage 3 held substantially parallel to y and moved two-dimensionally within the orthogonal coordinate system; a position measuring means 9 for measuring the coordinate position of the stage;
10, an exposure having an exposure center point at a predetermined position in an orthogonal coordinate system, and exposing a pattern area Pr overlapping the shot area when the exposure center point coincides with the center point of the shot area on the sensitive substrate. means R, 1, and mark detection means 30 to 3, which have a detection center point at a position unique to the exposure center point in the orthogonal coordinate system and detect marks on the sensitive substrate.
8, 41 to 48, the stage is moved so that any mark on the sensitive substrate is detected by the mark detection means, and the center point of any shot area on the sensitive substrate matches the exposure center point. The present invention relates to a positioning apparatus including control means 5, 6, and 50 for moving the stage so as to move the stage. The fourth invention of the present application further comprises: (a) storage means for storing design coordinate values Dn of the stage such that the center points of the plurality of shot areas coincide with the exposure center point; (b) mark detection means; using a position measuring means,
Each of the m shot areas is detected by detecting the coordinate values of the stage such that the mark attached to each of the m (m<n) shot areas on the sensitive substrate coincides with the detection center point. shot coordinate measurement means 50, 103, 104) for specifying the measured coordinate values of the stage for aligning the center point with the exposure center point; (c) sequentially exposing each of the plurality of shot areas with the pattern area of the exposure means; (d) m first calculating means 108 for calculating the movement coordinate value Fn of the stage when the stage is moved based on a relational expression uniquely expressed with predetermined coefficients A and O from the design coordinate value Dn; Each measured coordinate value of the shot area of
The coefficients of the first calculation means are calculated based on the measured coordinate values and the corresponding design coordinate values Dn so that each deviation from the movement coordinate values Fn corresponding to each of the m shot areas is minimized. A second calculation means 107 for calculating the value of is provided.

(Example) FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for implementing and measuring the method of the present invention. The reticle R serving as a projection original is positioned so that its projection center passes through the optical axis of the projection lens 1, and is mounted on the apparatus. The projection lens 1 reduces the circuit pattern image drawn on the reticle R to 1/5 or 1/10 and projects it onto the wafer WA. The wafer holder 2 vacuum-chucks the wafer WA and is provided so as to be minutely rotatable relative to a stage 3 that moves two-dimensionally in the x and y directions. A drive motor 4 is fixed on the stage 3 and rotates the wafer holder 2. Further, movement of the stage 3 in the x direction is performed by driving a motor 5, and movement in the y direction is performed by driving a motor 6. A reflecting mirror 7 whose reflecting plane extends in the y-direction and a reflecting mirror 8 whose reflecting plane extends in the x-direction are fixed to two orthogonal sides of the stage 3, respectively. Laser light wave interferometer (hereinafter simply referred to as laser interferometer) 9
projects a laser beam onto the reflecting mirror 8 to detect the position (or movement amount) of the stage 3 in the y direction, and a laser interferometer 10 projects a laser beam onto the reflecting mirror 7 to detect the position (or amount of movement) of the stage 3 in the x direction. Detect position (or amount of movement). To measure the projection lens 1, the wafer WA
Off-axis wafer alignment microscopes (hereinafter referred to as WAM) 20 and 21 are provided to detect (or observe) the alignment marks on the top. Note that the WAM 21 is located after the projection lens 1 in FIG. 1 and is not shown. WAM2
0 and 21 have optical axes parallel to the optical axis AX of the projection lens 1, respectively, and form strip-shaped laser spot lights YSP and θSP elongated in the x direction onto the wafer WA. (Spotlight YSP is not shown in Figure 1.)
These spot lights YSP and θSP have wavelengths that do not sensitize the photosensitive agent (photoresist) on the wafer WA, and in this embodiment, they vibrate in the y direction with minute amplitude. The WAMs 20 and 21 each have a photoelectric element that receives scattered light or diffracted light from the mark, and a circuit that synchronously rectifies the photoelectric signal with the vibration period of the spot light. An alignment signal is output according to the amount of deviation of the mark from the center in the y direction. Therefore WAM2
0 and 21 have a configuration equivalent to a so-called spot light vibration scanning type photoelectron microscope.

Now, this device is equipped with a wafer via the projection lens 1.
A laser step alignment (hereinafter referred to as LSA) optical system is provided to detect marks on the WA. The laser beam LB generated from a laser light source (not shown) and passed through an expander (not shown), a cylindrical lens, etc.
The light beam enters the beam and is split into two beams. One of the laser beams is reflected by the mirror 31, passes through the beam splitter 32, and passes through the imaging lens group 33.
After being converged into a spot light having a strip-shaped cross section, the light is incident on a first folding mirror 34 arranged between the reticle R and the projection lens 1 so as not to block the projection optical path of the circuit pattern. The first folding mirror 34 reflects the laser beam upward toward the reticle R. The laser beam is on the reticle R
The light enters a mirror 35 provided below the reticle R and has a reflection plane parallel to the surface of the reticle R, and is reflected toward the center of the entrance optical pupil of the projection lens 1. The laser beam from the mirror 35 is converged by the projection lens 1, and is imaged onto the wafer WA as a strip-shaped spot light LYS extending in the x direction. The spot light LYS scans a diffraction grating mark extending in the x direction on the wafer WA relatively in the y direction.
It is used to detect the position of the mark. When the spot light LYS illuminates a mark, diffracted light is generated from the mark. The optical information returns to the projection lens 1, mirror 35, mirror 34, imaging lens group 33, and beam splitter 34, is reflected by the beam splitter 34, and is sent to an optical element 36 consisting of a condensing lens and a spatial filter. incident. This optical element 36 receives the diffracted light (1
The diffracted light is passed through the mirror 37, and the specularly reflected light (0th order light) is blocked.
The light is focused on the light-receiving surface of the photoelectric element 38 via. The photoelectric element 38 outputs a photoelectric signal according to the amount of the collected diffracted light. As above, mirror 31, beam splitter 32, imaging lens group 33, mirrors 34, 3
5, optical element 36, mirror 37, and photoelectric element 3
8 constitutes a through-the-lens type alignment optical system (hereinafter referred to as Y-LSA system) that detects the position of the mark on the wafer WA in the y direction.

On the other hand, another laser beam split by the beam splitter 30 enters a through-the-lens alignment optical system (hereinafter referred to as the X-LSA system) that detects the position of the mark on the wafer WA in the x direction. . The X-LSA system is exactly the same as the Y-LSA system,
Consisting of a mirror 41, a beam splitter 42, an imaging lens group 43, mirrors 44 and 45, an optical element 46, a mirror 47, and a photoelectric element 48, a strip-shaped spot light LXS extending in the y direction is emitted onto the wafer WA. Form an image.

The main controller 50 inputs photoelectric signals from the photoelectric elements 38 and 48, alignment signals from the WAMs 20 and 21, and position information from the laser interferometers 9 and 10, and performs various calculation processes for alignment. At the same time, a command for driving the motors 4, 5, and 6 is output. This main controller 50 is equipped with an arithmetic processing section such as a microcomputer or a minicomputer, and the arithmetic processing section includes a wafer.
Design position information (chip arrangement coordinate values on wafer WA, etc.) of a plurality of chips CP formed on WA is stored.

Figure 2 shows the above WAM20, 21 and Y-LSA system,
Spot light θSP, YSP, LYS, by X-LSA system
FIG. 3 is a plan view showing the arrangement relationship on the imaging plane (same as the surface of the wafer WA) of the projection lens 1 of the LXS.
In Figure 2, the coordinate system xy whose origin is the optical axis AX
, the x-axis and y-axis are respectively at stage 3.
represents the direction of movement. In FIG. 2, the circular area centered on the optical axis AX is the image field if, and the rectangular area inside it is the projected image Pr of the effective pattern area of the reticle R. spot light LYS
is formed at a position outside the projected image Pr within the image field if and coincident with the x-axis, and the spot light LXS is also formed at a position outside the projected image Pr within the image field if.
It is formed to coincide with the y-axis at a position outside Pr. On the other hand, the vibration centers of the two spot lights θSP and YSP are aligned on a line segment (parallel to the x-axis) l spaced a distance Y ₀ from the x-axis in the y-direction, and the distance Dx in the x-direction is It is set to be a smaller value than the diameter of WA. In this device, the spot lights θSP, YSP are arranged symmetrically with respect to the y-axis, and the main controller 50 stores information regarding the positions of the spot lights θSP, YSP with respect to the projection point of the optical axis AX. Also, the main control device 50
is the center position (distance X1) of the spot light LYS in the x direction with respect to the projection point of the optical axis AX and the spot light
Information regarding the center position (distance Y1) of LXS in the y direction is also stored.

Next, the alignment method according to the present invention using this device will be explained along with the operation of the device using the flowchart shown in FIG. Note that this alignment is performed for the second and subsequent layers of the wafer WA, and chips and alignment marks have already been formed on the wafer WA.

First, in step 100, the wafer WA is roughly positioned using a pre-alignment device (not shown) so that the linear notch (flat) of the wafer WA is oriented in a fixed direction. The flat of wafer WA is positioned parallel to the x-axis as shown in FIG. Next, in step 101, the wafer is
The WA is transferred onto the wafer holder 2 of the stage 3, placed on the wafer holder 2 so that the flat remains parallel to the x-axis, and vacuum-adsorbed. On the wafer WA, for example, as shown in FIG. 4, a plurality of chips Cn are formed in a matrix along orthogonal arrangement coordinates αβ on the wafer WA. The α axis of the array coordinate αβ is approximately parallel to the flat of the wafer WA. In Fig. 4, among the plurality of chips Cn, α, which passes approximately through the center of the wafer WA with the array coordinates αβ, is representative.
Only chips C ₀ -C ₆ lined up on the axis are shown. Each chip C ₀ to _{C 6} is provided with four alignment marks GY, Gθ, SX, and SY, respectively. Now, when the center of chip C ₃ in the center of chips C ₀ to C ₆ is taken as the origin of the array coordinate αβ,
On the α axis, diffraction grating-like marks SY ₀ to _{SY 6} extending linearly in the α direction are provided on the right side of the chips C ₀ to _{C 6} , respectively. Also, on the β axis passing through the center of chip C ₃ , there is a diffraction grating mark extending linearly in the β direction.
SX ₃ is installed below chip C ₃ , and other chips
For C ₀ , C ₁ , C ₂ , C ₄ , C ₅ , and C ₆ , mark SX ₀ on the line passing through the center of the chip and parallel to the β axis.
~ _SX2 , _SX4 ~ _SX6 are provided. These marks SYn and SXn are Spotlight LYS, respectively.
This is what is detected by LXS. Marks GY ₀ to GY 6 and Gθ _{0 to} Gθ ₆ used for global alignment of the wafer WA are provided below each chip C ₀ to _{C 6} . These marks GYnGθn are formed in a diffraction grating pattern extending linearly in the α direction on line segments parallel to the α axis. Further, among the chips C ₀ to G ₆ arranged in the α direction, for example, the leftmost chip C ₀
The interval in the α direction between the mark GY ₀ of the chip C ₆ and the mark Gθ ₆ of the right-most chip C 6 is determined to match the interval DX of the spot lights θSPYSP from the WANs 20 and 21. That is, in this embodiment, global alignment of the wafer WA is performed in an off-axis manner using marks GY ₀ and Gθ ₆ located at two separate locations. For this reason other marks GY ₁ ~ GY ₆ , marks
Gθ ₀ to Gθ ₅ are originally unnecessary and may be omitted. The point is that two marks extending thin and thin in the α direction are spaced apart on a line parallel to (or coinciding with) the α axis of the wafer WA.
Only DX needs to exist separately.

Now, from the position information of the stage 3 when receiving the wafer WA from the main controller 50 pre-alignment device, the marks GY ₀ Gθ ₀ are
Information such as the direction and amount of movement of the stage 3 until it is located within the detection (observation) field of view of the WAMs 21 and 20 is stored in advance as constants specific to the apparatus. Therefore, in the next step 102, the main controller 50
First, drive motors 5 and 6, and mark GY ₀ is
The stage 3 is positioned within the detection field of the WAM 21. Then spot light
The main controller 50 precisely moves the stage 3 in the y direction based on the alignment signal from the WAM 21 and the position information from the laser interferometer 9 so that the vibration center of YSP coincides with the center of the mark GY ₀ in the y direction. Position. When the vibration center of the spot light YSP and the center of the mark GY ₀ coincide, the main controller 50 controls the motor 6 to WAM so that this state is maintained.
Mark Gθ ₆ is connected to WAN 20 while under servo (feedback) control using the alignment signal from 21.
The motor 4 is driven to rotate the wafer holder 2 as detected by the spot light θSP.
Furthermore, the main controller 50 servo-controls the motor 4 using the alignment signal from the WAM 20 so that the vibration center of the spot light θSP and the center of the mark Gθ ₆ in the Y direction coincide. Through the above series of operations,
The spot light YSP and the mark GY ₀ match, the spot light θSP and the mark Gθ ₆ match, and the wafer WA with respect to the moving coordinate system of the stage 3, that is, the coordinate system xy.
The rotational deviation of the array coordinate αβ of is corrected, and
The correspondence (definition) regarding the position of the coordinate system xy and the array coordinate αβ in the y direction (β direction) is completed. Next, the stage 3 is positioned so that the mark _SX3 of the chip _C3 located at the center of the wafer WA is scanned by the X-LSA spot light LXS, and then moved in the x direction. At this time, the main controller 50
is the wafer position when the mark SX ₃ coincides with the spot light LXS based on the time-series photoelectric signal from the photoelectric element 48 and the position information from the laser interferometer 10.
The position of WA in the x direction is detected and stored. This completes the correspondence between the coordinate system xy and the array coordinate αβ regarding the position in the x direction (α direction). Note that this x-direction mapping is performed immediately before the exposure operation.
It is not necessary when using the LSA system. Through the above operations, the global alignment of the wafer WA (corresponding to the coordinate system xy of the array coordinates αβ), which is mainly an off-axis type alignment, is completed. In the conventional method, the main controller 50 reads the position information from the laser interferometers 9 and 10 based on the array design value of each chip on the wafer WA (the chip center coordinate value in the array coordinate αβ). After positioning (addressing) the stage 3 by a step-and-repeat method so that the projected image Pr of the reticle R overlaps the chip, the chip is exposed (printed).

However, until the global alignment is completed, there may be variations in the position detection accuracy due to the accuracy of the alignment detection system, the setting accuracy of each spot light, or the optical and geometric condition of each mark on the wafer WA (effects of the process). Therefore, errors occur, and the chips on the wafer WA are not necessarily precisely aligned (addressed) according to the xy coordinate system. Therefore, in the embodiment of the present invention, the error (hereinafter referred to as a shock address error) is assumed to be caused by the following four factors.

(1) Wafer rotation; For example, when correcting the rotation of wafer WA,
Two spot lights YSP serve as alignment standards
This occurs because the positional relationship between and θSP is not accurate, and is expressed by the residual rotational error amount θ of the array coordinate αβ with respect to the xy coordinate system.

(2) Orthogonality with the coordinate system
It is expressed as the orthogonality error amount w.

(3) Linear expansion and contraction of the wafer in the x (α) and y (β) directions; this is caused by the processing process of the wafer WA.
This means that the wafer WA expands and contracts as a whole. For this reason, the actual chip position deviates by a minute amount in the αβ direction with respect to the designed arrangement coordinate values of the chip, which is particularly noticeable in the peripheral area of the wafer WA. The amount of expansion and contraction of the entire wafer is expressed by Rx and Ry in the α(x) direction and β(y) direction, respectively. However, Rx is the ratio between the actual measured value and the designed distance between two points in the x direction (α direction) on the wafer WA, and Ry is the ratio of the distance between two points on the wafer WA in the y direction (β direction).
It is expressed as the ratio of the measured value and the designed distance between two points. Therefore, when Rx and Ry are both 1, there is no expansion or contraction.

(4) Offset in the x (α) direction and y (β) direction; This depends on the detection accuracy of the alignment system, the positioning accuracy of the wafer holder 2, etc.
This is caused by the slight deviation of WA in the x and y directions, and is expressed by offset amounts Ox and Oy.

Now, in FIG. 4, the residual rotational error amount θ of the wafer WA and the orthogonality error amount w of the stage 3 are exaggerated.

In this case, the orthogonal coordinate system xy is actually a minute amount w
The wafer WA is rotated by θ with respect to the orthogonal coordinate system xy.
When the above error factors (1) to (4) are added, the shot position Fxn, Fyn that should be actually positioned for the shot (chip) at the coordinate position Dxn, Dyn in the design
is expressed as follows. However, n is an integer and represents a shot (chip) number.

Fxn Fyn=Rx, O O, Rycosθ, −sinθ sinθ, cosθ1, −tanw 0,1 Dxn Dyn +Ox Oy=Rx・cosθ, −Rx (cosθtanw+sinθ) Ry・sinθ, Ry (−sinθtanw+cosθ) Dxn Dyn+Ox Oy ……(1 ) Here, since w is originally an infinitesimal amount and θ is also reduced to an infinitesimal amount by global alignment, equation (1) can be expressed as equation (2) using first-order approximation.

Fxn Fyn=Rx, −Rx (w+θ) Ry・θ, RyDxn Dyn+Ox Oy ...(2) From this equation (2), the positional deviation (εxn, εyn) from the design value at each shot position is expressed by equation (3). expressed.

εxn εyn=Fxn Fyn−Dxn Dyn=Rx−1,−Rx(w+θ) Ry・θ, Ry−1Dxn Dyn+Ox Oy ……(3) Now, if we rewrite equation (2) as a matrix arithmetic equation, we get the following. become.

Fn=A・Dn+O ……(4) However, Fn=Fxn Fyn ……(5) A=a ₁₁ , a ₁₂ a ₂₁ , a ₂₂ = Rx, −Rx (w+θ) Ry・θ, Ry ……(6 ) Dn=Dxn Dyn...(7) O=Ox Oy...(8) Then, the actual shot (chip) position is measured by mark detection, and when the actual measured value is detected as Fn
The positional deviation with respect to the address error En = (−
The error parameters A (transformation matrix) and O (offset) are determined so as to minimize Fn). Therefore, if the least squares error is taken as the evaluation function, the address error E is expressed by equation (9).

E= _n 〓 ⁿ⁼¹ (Exn) ² + _n 〓 ⁿ⁼¹ (Eyn) ² = _n 〓 ⁿ⁼¹ (−Fxn) ² + _n 〓 ⁿ⁼¹ (−Fyn) ² ……(9) So, Error parameters A and O are determined so as to minimize address error E.

However, in equation (9), m represents the number of actually measured chips (shots) among the plurality of chips on the wafer WA.
Now, if the least squares method is used to obtain the error parameters A and O, the amount of calculation will be large as it is, so the error parameters O (Ox, Oy) are determined separately in advance. Since the offset amount (Ox, Oy) is a global offset value of the wafer WA, it is preferable to use a value that averages the address error with respect to the design value (Dxn, Dyn) over several meters of the actually measured chip position on the wafer WA.

By the way, the component Exn in the x direction of the error En between the shot position Fn to be positioned and the actual measurement value is:
From equations (4) to (8), Exn=−Fxn=−a ₁₁ Dxn−a ₁₂ Dyn−Ox
...(12) Similarly, the component Eyn in the direction of the error En is Eyn=−Fyn=−a ₂₁ Dxn−a ₂₂ Dyn−Oy
...(13) becomes. Therefore, if the error parameter A is determined to minimize the error E in equation (9), the elements a ₁₁ , a ₁₂ ,
a ₂₁ and a ₂₂ are as follows.

Once the elements a ₁₁ , a ₁₂ , a ₂₁ , and a ₂₂ are determined, the linear expansion/contraction amounts Rx, Ry, the residual rotation error amount θ, and the orthogonality error amount w are immediately determined from equation (6).

Rx＝a ₁₁ …(18) Ry＝a ₂₂ …(19) θ＝a ₂₁ /Ry＝a ₂₁ /a ₂₂ …(20) w＝−(a ₂₁ /Ry)−(a ₁₂ /Ry )=−(a ₂₁
/a ₂₂ ) - (a ₁₂ /a ₁₁ )...(21) Therefore, in order to determine the error parameters A and O, for some (4 or more) chips on the wafer WA after global alignment, X-
Mark SXn, SYn using LSA system and Y-LSA system
In addition to actually measuring the position of and finding the actual measured value (,), the actually measured design value of the chip (Dxn,
Dyn) to perform the calculations of equations (10), (11), and (14) to (17).

Therefore, returning to the flowchart of FIG. 3, the explanation of the operation will be continued. After the global alignment is completed, the main controller 50 measures the positions of the plurality of chips on the wafer WA. First, in step 103, the main controller 50 controls the X-LSA system spot light LXS.
is the mark attached to the leftmost chip C ₀ in Figure 4.
After positioning the stage 3 based on the array design values so that it is aligned parallel to SX ₀ , the stage 3 is moved (scanned) by a certain amount in the x direction so that the mark SX ₀ crosses the spot light LXS. During this move,
The main controller 50 stores the time-series photoelectric signal waveform of the photoelectric element 48 in association with the x-direction position information from the laser interferometer 10, and marks it based on the waveform state.
The position x ₀ at the time when SX ₀ and the spot light LXS coincide in the x direction is detected.

Next, in step 104, the main controller 50
The stage 3 is positioned based on the array design values so that the LSA-based spot light LYS is lined up parallel to the mark SY ₀ attached to the chip C ₀ . then mark
Stage 3 as SY ₀ crosses the spot light LYS
Move by a certain amount in the y direction. At this time, the main controller 50 stores the time-series photoelectric signal waveform of the photoelectric element 38 in association with the position information in the y direction from the laser interferometer 9, and from the waveform state marks SY ₀ and spot light LYS are determined. Detect the position y ₀ of the coincident point in time in the y direction. Then, in step 105, the main controller 50 determines whether or not similar position detection has been performed for m chips. Based on this, the stage 3 is moved and the same position detection operation is repeated again from step 103. In this embodiment, for example, as shown in FIG. 5, four chips C 0 , C ₀ ,
It is assumed that the position detection in steps 103 and 104 is performed for each of five chips in total, C ₆ , C ₇ , C ₈ and the central chip C ₃ . Therefore step 1
When it is determined that m=5 in 05, the main controller 50
Five actual measured values (,) are stored in . That is, ( ₁ , ₁ ) = (x ₀ , y ₀ )...Chip C ₀ ( ₂ , ₂ ) = (x ₃ , y ₃ )... Chip C ₃ ( ₃ , ₃ ) = (x ₆ , y ₆ )... Chip C ₆ ( ₄ , ₄ ) = (x ₇ , y ₇ )... Chip C ₇ ( ₅ , ₅ ) = (x ₈ , y ₈ )... Five actual measured values of chip C ₈ are sequentially detected. When detecting these five measured values, if the measured value of a certain chip is significantly different from the design value (Dxn, Dyn) of that chip, for example, the positioning accuracy determined by global alignment may be twice as high. If there is a difference as described above, the actual measurement value for that chip may be ignored and, for example, the actual measurement of the mark position may be performed for a chip adjacent to that chip. This is because if the mark on the chip that you are trying to measure happens to be deformed during the processing process, or if there is dust attached to that mark, the contrast of the optical image of that mark (the intensity of diffracted light generated) will be weak, and the photoelectric signal will be weak. This is to compensate for the deterioration in accuracy of position measurement that occurs when the S/N ratio is low. In addition, as a method to compensate for the deterioration in the accuracy of position measurement, it is possible to measure the position of six or more chips in advance, for example, by adding the chips located at each of the four phenomena of array coordinates αβ in Fig. 5, for a total of nine chips. The design value (Dxn, Dyn) of each chip was determined from the nine actual measured values.
There is a method of selecting five measured values in the order of closest to , or a method of simply not using measured values (,) that are significantly different from the design values (Dxn, Dyn) in subsequent arithmetic processing.

Next, in step 107, the main controller 50 determines error parameters A and O based on the above equations (10), (11), and equations (14) to (17). In making this decision, the main controller 50 selects in advance five design values for each chip that detected the five actual measured values, and stores the design values (Dxn, Dyn) as follows. It is assumed that there is

(Dx ₁ , Dy ₁ ) = (x ₀ ′, y ₀ ′)…Chip C ₀ (Dx ₂ , Dy ₂ ) = (x ₃ ′, y ₃ ′)…Chip C ₃ (Dx ₃ , Dy ₃ ) = (x ₆ ′, y ₆ ′)…Chip C ₆ (Dx ₄ , Dy ₄ ) = (x ₇ ′, y ₇ ′)…Chip C ₇ (Dx ₅ , Dy ₅ ) = (x ₈ ′, y ₈ ′ )...Chip C ₈ Also, prior to determining the actual error parameters A and O, each time the position measurement of each of the five chips (so-called step alignment) is completed, the stage 3 is moved in step 106 in Fig. 3, for example. While there, the ceremony
Some of the operations (10), (11), and (14) to (17) can be executed simultaneously. That is, equation (10),
In (11), (14) to (17), the calculation element representing the algebraic sum of the data (actual measurement value, design value) for each chip is calculated every time the actual measurement (step alignment) of one chip is completed. Add sequentially. The calculation elements are as follows. _n 〓 ⁿ⁼¹ Dxn, _n 〓 ⁿ⁼¹ Dyn, _n 〓 ⁿ⁼¹ , _n 〓 ⁿ⁼¹ , _n 〓 ⁿ⁼¹ Dxn ² , _n 〓 ⁿ⁼¹ Dyn ² , _n 〓 ⁿ⁼¹ Dxn・Dyn , _n 〓 ⁿ⁼¹ Dxn・, _n 〓 ⁿ⁼¹ Dxn・, _n 〓 ⁿ⁼¹ Dyn・, _n 〓 ⁿ⁼¹ Dyn・ (However, in this example, m=5) Furthermore, among these calculation elements, the wafer If the chip to be measured on the WA is determined in advance and there is no change, steps 103 and 10 in FIG.
It can also be calculated before executing steps 4, 105, and 106. If some calculations are performed in parallel with the actual measurement operation in this way, the overall alignment time will not be so long. and,
At the stage when the five actual measured values are obtained, the main controller 50 uses the results of the above calculation elements to calculate the offset amounts (Ox, Oy) using equations (10) and (11), and then calculates the offset values and the above values. Using the results of the calculation elements, array elements a ₁₁ , a ₁₂ , a ₂₁ , and a ₂₂ are further calculated using equations (14) to (17). Since the error parameters A and O are determined by the above calculation operation, the main controller 50 uses the above equation (4) in the next step 108 to calculate the wafer
The position to be positioned for each WA chip, that is, the shot address (Fxn, Fxy) corrected by the error parameters, is calculated and stored in the storage means (semiconductor memory) relative to the design value (Dxn, Dyn). Create a corrected chip arrangement map (shot address table). For example, for chip C ₀ , this array map contains the position (Fx ₀ , Fy ₀ ), chip
For C ₁ , each position data is stored in correspondence with the chip number, such as position (Fx ₁ , Fy ₁ ), etc.

Next, the main controller 50 performs step 109 in FIG.
At this step, the stage 3 is positioned (addressed) using a step-and-reheat method according to the stored array map. This allows the wafer to
The chip on WA and the projected image Pr of the reticle R overlap accurately, and in the next step 110, the projected image Pr is exposed (printed) on the chip. If the exposure of all chips on the wafer WA is not completed in step 111, the same step-and-repeat operation is repeated from step 109.
If it is determined in step 111 that all chips on the wafer WA have been exposed, the next step 1 is performed.
At step 12, the wafer WA is unloaded, and all exposure processing for one wafer is completed.

As is clear from the above embodiments of the present invention,
As the number of chips step-aligned on the wafer WA increases, the measurement accuracy improves, but the measurement time increases accordingly. Therefore, from the viewpoint of reducing measurement time and improving measurement accuracy, it is desirable to select five chips for step alignment as shown in FIG. However, if the minimum line width of the circuit patterns to be overlaid and exposed is not so thin (e.g. 2 to 5 μm) and there is no need to improve measurement accuracy, three chips separated from each other on the wafer WA (e.g. C ₀ , C ₆ , C ₇ )
It is sufficient to perform step alignment (measurement of the position of the chip), and the measurement time can be further shortened.

In addition, during step alignment, instead of detecting the position of each chip in both the x and y directions, the marks SXn attached to multiple chips to be step aligned are detected at once using the X-LSA spot light LXS. After performing relative scanning (stage scan) to detect only the position of each chip in the x direction, each mark SYn of each chip is subjected to Y-LSA.
The position of each chip in the y direction may be detected by performing relative scanning all at once using the spot light LYS of the system. In this way, when there are multiple chips to be measured in the same column or row on the chip array, position detection in the x and y directions is performed for each individual chip. We can expect measurements.

Furthermore, if the main controller 50 is configured to input data for arbitrarily selecting which chip on the wafer W to perform step alignment from a keyboard device (not shown), the surface state of the wafer WA changes depending on the processing conditions. (especially mark shapes), and can be expected to improve the accuracy of position measurement. Also, when determining the offset amount (Ox, Oy) using equations (10) and (11), use only the position measurement results of chips within a specified range from the center of the wafer WA, for example. Good too. For example, the specified range is wafer
Exposure equipment (reduced projection type, 1x projection type, proximity type, etc.) used when forming chips or marks on the wafer WA. ) may be arbitrarily varied according to the accuracy characteristics of

Furthermore, in this embodiment, step-and-repeat addressing is performed by applying equation (4) to all chips on the wafer WA, but the surface of the wafer WA is divided into several areas (blocks). Equation (4) can be applied in exactly the same way to so-called block alignment, which performs optimal alignment for each block. For example, in FIG. 5, there are four chips located within each phenomenon with array coordinates αβ, and five chips C ₀ , C 3 , C ₃ ,
After performing step alignment for a total of nine chips, C ₆ , C ₇ , and C ₈ and detecting the actual measured value of the position of each chip, the formula for each quadrant of array coordinates αβ is
The error parameters A and O are determined using (10), (11), and (14) to (17), and the position (Fxn, Fyn) is calculated using equation (4). For example, for a block in the first quadrant with array coordinates αβ, one chip in the first quadrant and chips C ₃ , C ₆ , C ₇
Equation (4) _is determined using _the measured values _of the four chips in the second quadrant. Equation (4) is determined using the measured values of the two chips. Then, during actual exposure, the chips on the wafer WA are aligned with the projected image Pr based on the shot position (Fxn, Fyn) from equation (4) determined for each block. By doing this, defects in position detection and alignment due to nonlinear elements on the wafer are reduced, and unlike conventional block alignment, blocks can be created while leaving the averaging element, so overlapping within each block can be reduced. It has the advantage that the alignment accuracy is almost average for all chips. In addition, great advantages can be obtained when the present invention is used in combination with an exposure apparatus other than a stepper, especially a mirror projection exposure apparatus. Generally, the chip array of a wafer printed with a mirror projection exposure apparatus is often curved. Therefore, when overlapping exposure is performed on the wafer using a stepper (mixed use;
If the above-described block alignment is performed, the curvature of the chip arrangement within each block becomes negligibly small, making it possible to print with extremely high overlay accuracy over the entire wafer.

As described above, in the exposure apparatus suitable for the embodiment of the present invention, the position of the mark (chip) is detected by irradiating the laser spot light onto the mark on the wafer WA. Alignment system that allows constant speed linear scanning,
Alternatively, a so-called die-by-die alignment optical system may be used to align the marks on the reticle R and the marks on the wafer WA by observing (detecting) them through a microscope objective lens placed above the reticle R. The process can be carried out in exactly the same manner using an exposure apparatus. In this case, if the reticle R is not slightly moved in the x and y directions for alignment during die-by-die alignment, the projected image of the mark on the reticle R will be the same as the spot lights LXS and LYS of this embodiment. It will be equivalent. In addition, in the case of a method in which the reticle R is moved slightly, the reticle R is first set so as to be accurately aligned with the origin position. During step alignment (actual measurement) of multiple chips, after stepping the stage according to the array design values, the reticle R
By slightly moving the reticle R so that the mark on the chip and the mark on the chip to be measured are in a predetermined positional relationship, and detecting the amount of movement of the reticle R in the x and y directions from the origin, the chip can be measured. The actual measured value (,) of the position can be calculated.

Furthermore, in this embodiment, the offset amounts (Ox, Oy) are calculated separately to simplify the calculation process, but the error parameters A, O that minimize the address error E in the following (9) are Needless to say, may be calculated by strict arithmetic processing.

(Effects of the Invention) As described above, according to the present invention, the alignment error is reduced on average for all of a plurality of chip patterns (shot areas) formed on a substrate such as a wafer. The greater the number of good quality chips produced, the greater the effect. In addition, when sequentially aligning multiple areas on the substrate with respect to the processing center point, inspection center point, or exposure center point, the stage is adjusted based on estimated values from the actually measured coordinate positions of several areas. Since it is only moved, the throughput is higher than that of a method in which coordinate positions are actually measured for each area on the substrate and alignment is performed. Furthermore, the coordinate positions of several actually measured areas are calculated to determine the coefficients A and O of the unique relational expression (Fn=A・Dn+O), but when moving the stage sequentially during actual measurement, There is also the advantage that mechanical or electrical random errors that occur are averaged out by calculation, and that the coefficients A and O are less susceptible to such random components.

Furthermore, according to the embodiment, since the least squares method is used to determine the error parameters, it is possible to suppress variations in step alignment accuracy for several chips. Note that the present invention is not limited to reduction projection type exposure apparatuses, but can be widely applied to step-and-repeat type exposure apparatuses, such as life-size projection type steppers and proximity type steppers (X-ray exposure apparatuses). . In addition to exposure equipment, equipment (defect inspection, prober, etc.) that inspects semiconductor wafers, photomasks with multiple chip patterns, etc. uses a step-and-repeat method for each chip to adjust the inspection field of view and the reference position of the probe needle, etc. The present invention can be implemented similarly in the case of alignment.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for an embodiment of the present invention, and FIG. 2 is a plan view showing the positional relationship of each detection center of the alignment system in the apparatus shown in FIG. , FIG. 3 is a flowchart showing the overall operating procedure using the alignment method of the present invention, and FIG. 4 is a flowchart showing the overall operating procedure using the alignment method of the present invention.
FIG. 5 is a plan view of a wafer suitable for alignment and exposure. FIG. 5 is a plan view of a wafer showing the positions of chips to be step aligned. [Explanation of symbols of main parts], WA...Wafer,
CP, Cn... Chip, αβ... Array coordinates, 103,
104... 8 actual measurement steps by step alignment, 107... Step of determining error parameters,
108, 109, 110, 111 . . . Steps of positioning by step-and-repeat method along the corrected actual chip arrangement coordinates.

Claims (1)

[Claims] 1. A method for sequentially aligning each of a plurality of chip patterns regularly arranged on a substrate to be processed along designed arrangement coordinates with respect to a predetermined reference position using a step-and-repeat method. , prior to alignment in the step-and-repeat direction, the substrate to be processed is moved based on the designed arrangement coordinate values of the chip patterns, and some of the plurality of chip patterns are aligned with the reference position. an actual measurement step of actually measuring each position; the designed array coordinate values and the actual array coordinates to be aligned by the step-and-repeat method are assumed to have a unique relationship including a predetermined error parameter; a first calculation step of determining the error parameter so that an average deviation between the plurality of measured values and the actual array coordinate value is minimized; the determined error parameter and the designed array; a second calculation step of calculating the actual array coordinate values based on the coordinate values; during step-and-repeat alignment; An alignment method comprising the step of positioning a substrate to be processed. 2. When the substrate to be processed is divided into a plurality of block regions, performing the actual measurement step, the first calculation step, and the second calculation step on several chip patterns existing in one block region of interest; When aligning each chip pattern within the block area of interest using the step-and-repeat method, the positioning step is performed in accordance with the actual array coordinate values calculated in the second calculation step with respect to the area of interest. A method according to claim 1, characterized in that: 3 A substrate WA on which a plurality of processed regions Cn are regularly formed in two dimensions is arranged so that the arrangement coordinates (α, β) of the processed regions are almost parallel to a predetermined orthogonal coordinate system x, y. a stage 3 that is held so that
and the machining center point at a predetermined position within the orthogonal coordinate system.
A processing means R,1 having an AX and processing a processing area of the substrate on the stage, and one of the specific points set inside each of the plurality of processing areas with respect to the processing center point. In an alignment apparatus comprising control means 5, 6, and 50 for controlling the movement of the stage so as to lead to a predetermined positional relationship, (a) the design arrangement coordinates (α , β) for storing design coordinate values Dn of the stage 3 that lead each specific point of the plurality of work areas Cn to the processing center point AX; By actually measuring the coordinate position of each specific point of m (however, m<n) mutually different work areas among the work area Cn of , based on the measurement values of the position measuring means 9 and 10, Each specific point of the m workpiece areas is the machining center point.
Actual measurement means 30 to 38, 41 to specify coordinate values of the stage 3 to match with AX
48, 50, 103, 104; (c) moving coordinate values Fn of the stage 3 for aligning each specific point of the plurality of work areas Cn with the machining center point AX to the design coordinate value Dn; (d) a first calculation means 108 that calculates Fn=A・Dn+O using predetermined error parameters A and O; ,
Based on each of the design coordinate values Dn corresponding to each of the m workpiece regions, the deviation between each of the measured coordinate values and the movement coordinate value Fn is calculated for each of the m or less actually measured workpiece regions. and a second calculation means 107 for calculating the values of the error parameters A and O to minimize them, and the control means calculates the values of the error parameters A and O so as to minimize them, and the control means uses the calculated values of the error parameters A and O to A positioning device characterized in that the stage 3 is sequentially moved to determined movement coordinate values Fn. 4. The actual measurement means includes the plurality of processing areas Cn
4. The apparatus according to claim 3, wherein coordinate values of each of m specific points of three or more machining areas, which are less than n and are at least n, are actually measured. 5. The second calculation means includes means for determining whether or not the actually measured coordinate values of each specific point of the m workpiece regions have been obtained almost normally, and the actually measured coordinate values that have not been normally obtained. 5. The apparatus according to claim 3, further comprising means for excluding the error parameters A and O from calculation of the values of the error parameters A and O. 6. When it is determined that the actually measured coordinate values have not been obtained normally, the actual measuring means measures the actually measured coordinate values for another workpiece area located in the vicinity of the workpiece area in which the abnormal actually measured coordinate values have been detected. The device according to claim 3 or 4, characterized in that it detects. 7 The processing means includes a reticle R provided with a pattern region Pr to be superimposed on one processing region on the substrate, and cooperates with the stage to move the pattern region of the reticle R into a plurality of processing regions on the substrate. 7. The apparatus according to any one of claims 3 to 6, wherein each processing area is exposed by a step-and-repeat method. 8 The first calculation means divides the movement coordinate value Fn and the design coordinate value Dn into values in each coordinate axis direction of the orthogonal coordinate system (x, y), and calculates Fn=
(Fxn, Fyn), Dn=(Dxn, Dyn), and when the error parameters A and O are vectors, Fxn Fyn=a ₁₁ a ₁₂ a ₂₁ a ₂₂ Dxn Dyn+Ox Oy is calculated, and the second Claim 3 or 7, wherein the calculation means calculates at least four elements a ₁₁ , a ₁₂ , a ₂₁ , and a ₂₂ of the error parameters by a least squares method. The device described in. 9 A substrate WA on which a plurality of regions Cn are regularly formed in two dimensions is arranged so that the arrangement coordinates (α, β) of the regions are almost parallel to a predetermined orthogonal coordinate system (x, y). and 2 in the orthogonal coordinates.
It has a stage 3 that moves dimensionally, position measuring means 9 and 10 that measures the coordinate position of the stage, and an inspection center point AX at a predetermined position within the orthogonal coordinate system,
Inspection means R,1 for inspecting a region of the substrate on the stage, and one of the specific points set inside each of the plurality of regions is guided to a predetermined positional relationship with respect to the inspection center point. In the positioning apparatus comprising control means 5, 6, and 50 for controlling the movement of the stage, (a) the designed arrangement coordinates (α,
(b) storage means for storing design coordinate values Dn of the stage 3 that lead each specific point of the plurality of regions Cn to the inspection center point AX based on β); By actually measuring the coordinate position of each specific point in m (m<n) different regions among them based on the measurement values of the position measuring means 9 and 10, each of the m regions is actual measurement means 30 to 38, 41 to 48, 50, 103 for specifying coordinate values of the stage 3 to match a specific point with the inspection center point AX;
104; (c) A predetermined value is calculated based on the design coordinate value Dn to calculate a movement coordinate value Fn of the stage 3 for aligning each specific point of the plurality of regions Cn with the inspection center point AX. error parameter A,
a first calculation means 108 that calculates Fn=A・Dn+O using
Based on each of the design coordinate values Dn corresponding to each of the m or less actually measured regions, the Second calculation means 1 for calculating values of error parameters A and O
07, and the control means sequentially moves the stage 3 to the movement coordinate value Fn determined by the first calculation means 108 using the calculated error parameters A and O. Alignment device. 10 A plurality of shot areas Cn arranged two-dimensionally according to predetermined array coordinates (α, β), and accompanying each of the plurality of shot areas, a positional relationship that coincides with the center point of each shot area. mark to be placed
a stage 3 that holds the sensitive substrate WA on which SXn and SYn are formed so that the array coordinates are substantially parallel to a predetermined orthogonal coordinate system x, y, and moves the sensitive substrate WA two-dimensionally within the orthogonal coordinate system; Position measuring means 9 and 10 for measuring the coordinate position of the stage, and an exposure center point at a predetermined position within the orthogonal coordinate system, and the exposure center point and the center point of the shot area on the sensitive substrate coincide with each other. At this time, an exposure means R,1 for exposing a pattern area Pr overlapping with the shot area, and a detection center point located at a position unique to the exposure center point in the orthogonal coordinate system, and a mark on the sensitive substrate are provided. Mark detection means 30 to 38, 41 to 48 to detect
and moving the stage so that an arbitrary mark on the sensitive substrate is detected by the mark detection means, and the center point of an arbitrary shot area on the sensitive substrate coincides with the exposure center point. In the positioning apparatus comprising control means 5, 6, and 50 for moving the stage as shown in FIG. (b) m (where m<n) on the sensitive substrate using the mark detection means and the position measurement means;
By detecting coordinate values of the stage such that the mark attached to each of the m shot areas coincides with the detection center point, the center point of each of the m shot areas can be set as the exposure center point. Actual coordinate values of the stage for matching
Shot coordinate measurement means 50, 1 for specifying Fn
03, 104; (c) The movement coordinate value Fn of the stage when sequentially exposing each of the plurality of shot areas with the pattern area of the exposure means is set to the design coordinate value Dn.
A first calculating means 10 that calculates based on a relational expression uniquely expressed with predetermined coefficients A and O from
(d) The actual measurement is performed so that each deviation between each actual measurement coordinate value of the m shot areas and the movement coordinate value Fn corresponding to each of the m shot areas is minimized. the first coordinate value based on the coordinate value and the corresponding design coordinate value Dn;
Second calculation means 1 for calculating the value of the coefficient of the calculation means
07. An alignment device characterized by comprising: