JP2822229B2 - Positioning method and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an alignment method and an apparatus therefor, and more particularly, to a plurality of rectangular regions (chip patterns).
Are aligned relative to a predetermined reference point and a substrate formed regularly in the x and y directions, for example, in a step-and-repeat type projection exposure apparatus, a proximity X-ray exposure apparatus, etc. TECHNICAL FIELD The present invention relates to a method and an apparatus for relative positioning between a conductive substrate (semiconductor wafer, liquid crystal plate, etc.) and a reticle or a mask.

[Conventional technology]

This kind of conventional alignment method (alignment method)
First, as disclosed in Japanese Patent Application Laid-Open No. 61-44429, alignment is performed before exposure on a representative number of chip patterns among a plurality of chip patterns formed on a wafer. A method is known in which the arrangement state of the chip patterns on the wafer is determined by a linear error parameter with respect to the arrangement coordinates in the design, and the position of each chip pattern with respect to the reticle (or mask) is determined based on this. I have. Secondly, a method of measuring the relative positional deviation of a chip pattern with respect to a reticle (or mask) for each exposure of each chip pattern and performing alignment of individual chip patterns based on the measured value is disclosed in, for example,
This is known from JP-A-60-130742.

The first method disclosed in Japanese Patent Application Laid-Open No. 61-44429 is an extension of the global alignment method for wafers, and is called EGA (Enhanced Global Alignment) or AGA (Advanced Global Alignment). . In the second method disclosed in Japanese Patent Application Laid-Open No. Sho 60-130742, the position shift is measured for each chip pattern, and the exposure is repeated after correcting the position error. Alignment method (ESA method),
Or, it is called a die-by-die alignment method (D / DA method). These shots and dies correspond to chip patterns on a wafer.

Therefore, the first method and the second method are described in the twelfth.
This will be briefly described with reference to the drawings.

FIG. 12 (A) shows a second method, namely, each shot shot.
1 illustrates an alignment (ESA) method. Usually, since the wafer is circular, a chip is present at the periphery. In the step-and-repeat type exposure apparatus (stepper), there are a case where all chip patterns including the missing chip are exposed and a case where only a normal chip pattern excluding the missing chip is exposed. In addition, on wafers that are premised on the processing by the each shot alignment method, an alignment mark is provided for each chip pattern.
Mx and My are formed in a predetermined positional relationship with respect to the chip center. The mark Mx is for detecting the position of the chip in the x direction (direction parallel to the wafer orientation flat), and the mark My is for detecting the position of the chip in the y direction.

When a chip is also exposed by the step-and-repeat method, the pattern projection image of the reticle is located at the point P ₀ (the center point on the design value of the chip) as shown in FIG. The wafer stage is positioned as described above. For this chipping chip, since the alignment mark is not present, as it is after the exposure of the reticle pattern, and the next chip patterns C ₁ and the reticle pattern projected image is stepping predetermined amount the stage as substantially overlap. Since the chip pattern C ₁ is missing chips, wherein the mark Mx, since there is no point performs alignment using the My, performed directly exposed again. Thus,
Exposure is repeated by performing stepping in the order of chip patterns C ₁ , C ₂ , C ₃ , C ₄ , and C ₅ . Next, the center point P ₁ of the missing chip on the left of the chip pattern C ₅ , the center point P of the missing chip diagonally lower left
₂ stepping sequentially, exposure, then repeats stepping and exposure in the order of chip patterns C ₆ chip pattern C ₇ to _{right, C 8, C 9, C} 10, C 11, C 12. At this time, since the chip pattern C ₇ is a normal chip without missing mark when the stepping Mx, the exposure from the precisely aligned with the reticle pattern image and the chip pattern C ₇ performs position detection of My Do. Alignment is similarly performed for the chip patterns C ₈ , C ₉ , C ₁₀ , and C ₁₁ . That is all
Although this is one sequence of the shot alignment method, even if a chip is missing, the alignment mark Mx, My
There is also a sequence in which alignment is performed for a chip pattern in which both are present. In that case, each chip pattern C ₁ -C ₄ is missing chips, and alignment is performed for the chip patterns _{C 6, C 12, C 13} . As described above, there are several variations of the stepping sequence of the each shot alignment method, but basically, selection of whether or not to expose a missing chip and selection of whether or not a mark exists even in the missing chip. This is a combination of selection of whether or not to perform alignment. In selecting whether or not to perform alignment, it is also possible to select if at least one mark is present on a chip that is missing. Also in Fig. 12 (A), the stepping of the chip patterns C ₁₂ to C _13, shows the case where to the right of the missing chip chip patterns C _12, designated not to perform exposure. Also, in the figure, ○ indicates a normal chip, and ● indicates a chip that is missing.

On the other hand, according to the first method disclosed in Japanese Patent Application Laid-Open No. 61-44429, a circle EC having a predetermined radius is set on a wafer as shown in FIG. A plurality of chips located substantially at the vertices of a regular polygon, for example, seven chip patterns C ₉ , C ₁₄ , C ₁₅ , C ₁₆ , C ₁₇ , C ₁₈ , and C ₁₉ are designated, and the mark Mx is set for the seven chip patterns. , My position is measured by the alignment sensor. Then, using these position measurement values and design values, error parameters (shifts in the x and y directions, wafer rotation, orthogonality of the array, and expansion and contraction) relating to the array characteristics of the chip pattern are calculated using a least square method or the like. I do. When the error parameter is obtained, the stepping coordinate value obtained by correcting the design chip pattern coordinate value based on the parameter is calculated for all chip patterns to be exposed, so that the wafer is located at the calculated coordinate value. Exposure is repeated by sequentially stepping the wafer stage. Therefore, the position detection operation using the marks Mx and My has been completed before the exposure operation of the step-and-repeat method, and the throughput is several times as compared with the second method (each shot alignment). Step up. Moreover, unlike the conventional global alignment method,
Since the arrangement characteristics of the chip patterns are recognized with high accuracy, there is an advantage that the alignment accuracy is extremely good even for other chip patterns for which alignment (mark position detection) has not been performed.

In FIG. 12 (B), the circle EC is set such that the chip pattern to be aligned is located one inward from the outermost periphery of the wafer.

[Problems to be solved by the invention]

However, each position coordinate of the actual chip pattern formed on the wafer includes a random position error with respect to the design position coordinates. Further, when measuring the alignment marks of individual chip patterns, there are random measurement errors due to shape distortion of the marks themselves, noise included in the measurement system, and the like. If the random position error is relatively small with respect to the random measurement error, the first method (EGA method) is advantageous, and if the reverse, the second method (ESA method) is advantageous. In other words, the first EGA method has a drawback that it is directly affected by a random position error, and the second ESA method has a drawback that it is directly affected by a random measurement error. In an actual process wafer, both of these two types of errors often exist in a non-negligible amount, and even if either method is selected and used, it is possible to prevent a decrease in alignment accuracy. Did not.

The present invention has been made in view of the above points, and a high-accuracy alignment method that minimizes the influence of random position errors in the chip pattern arrangement and random position errors included in alignment mark detection is provided. It is intended to provide.

[Means for solving the problem]

In order to solve the above problem, in the present invention, measurement for determining the arrangement state of chip patterns (shot areas) is first performed in the same manner as in, for example, the method disclosed in JP-A-61-44429. , Data including a linear error parameter with respect to the chip pattern arrangement coordinates in the design. In addition, a statistical value of a random position error with respect to an array coordinate in the design of the chip pattern and a statistical value of a random measurement error included in a measurement value when a mark position of the chip pattern is measured are given as data in advance. A position estimation filter (arithmetic expression) based on the law of least squares estimation is constructed from the data of these two statistics and the coordinate data predicted from the design position using the linear error parameter.

Next, the measured position coordinates (actually measured coordinate values) obtained by sequentially aligning the chip patterns are input to the previously set position estimating filter, and the chip position estimated value (estimated coordinate) which is the output value of the filter is input. Value) is a technical point.

(Operation)

According to the present invention, the random error component is divided into two, that is, the position error of the chip array and the measurement error at the time of measurement. Predicted coordinate value of chip pattern whose estimation filter is determined by EGA method Measured coordinate value obtained by weighting or by ESA method Determines whether to apply weight to.

That is, the position estimation filter is E. when the random array error is relatively large compared to the random measurement error.
A value close to the alignment result (actually measured coordinate value) by the SA method is output as an estimated coordinate value, and in the opposite case, a value close to the alignment result (predicted coordinate value) by the EGA method is output as an estimated coordinate value. Of course, the estimated coordinate value of the intermediate value is also output.

The random array position error and the random measurement error are obtained in advance as standard deviations (σ _u , σ _w ), and weight coefficients are set using the standard deviations.

According to the present invention, several chip patterns are sample-aligned by the EGA method, and predicted coordinate values of the chip patterns determined based on the result are determined. And the measured coordinate values detected by ESA method Coordinate values that are estimated to have the least effect of random error between Is determined, high-accuracy alignment can be realized in which the disadvantage of the EGA method (weak to random alignment errors) and the disadvantage of the ESA method (weak to random measurement errors) are compensated for each other.

〔Example〕

FIG. 2 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus (stepper) suitable for carrying out the method of the present invention. The reticle R serving as a projection master is positioned such that the projection center (the center point of the circuit pattern area) passes through the optical axis of the projection lens 1 and is mounted on the apparatus. The one-sided (or both-sided) telecentric projection lens 1 reduces the circuit pattern image drawn on the reticle R to 1/5 or 1/10 and projects it on the wafer WA. The wafer holder 2 is provided so as to be capable of micro-rotation with respect to the stage 3 which vacuum-adsorbs the wafer WA and two-dimensionally moves in the X and Y directions. The drive motor 4 is fixed on the stage 3 and rotates the wafer holder 2. The movement of the stage 3 in the X direction is performed by driving the motor 5, and the movement in the Y direction is performed by driving the motor 6. Stage 2 orthogonal 2
A reflection mirror 7 having a reflection plane extending in the Y direction and a reflection mirror 8 having a reflection plane extending in the X direction are fixed to the sides. A laser light wave interferometer (hereinafter, simply referred to as a laser interferometer) 9 projects a laser beam onto the reflection mirror 8 to change the position (or the amount of movement) of the stage 3 in the Y direction by, for example, 0.02 μm.
m, and the laser interferometer 10 projects the laser beam onto the reflection mirror 7 to detect the position (or the amount of movement) of the stage 3 in the X direction with the same resolution. In order to detect (or observe) alignment marks on the wafer WA, off-axis type wafer global alignment microscopes (hereinafter referred to as WGA) 20, 21 are provided on the sides of the projection lens 1.
Is provided. The WGA 21 is located behind the projection lens 1 in FIG. 1 and is not shown. Each of the WGAs 20 and 21 has an optical axis parallel to the optical axis AX of the projection lens 1, and forms an elongated strip-shaped laser spot light YSP or θSP elongated in the X direction on the wafer WA. (The spot light YSP is not shown in FIG. 1.) These spot lights YSP and θSP are lights having a wavelength that does not expose the photosensitive agent (photoresist) on the wafer WA. Is oscillating. And
Each of the WGAs 20 and 21 has a photoelectric element for receiving scattered light and diffracted light from a mark, and a circuit for synchronously rectifying the photoelectric signal with the oscillation cycle of the spot light, and the center of oscillation of the spot light θSP (YSP) in the Y direction. And outputs an alignment signal corresponding to the amount of shift of the mark in the Y direction with respect to. Therefore, the WGAs 20 and 21 have the same configuration as a so-called spot light vibration scanning type photoelectric microscope. Further, the apparatus includes a wafer WA through a projection lens 1.
A laser step alignment (hereinafter referred to as LSA) optical system for detecting the upper mark is provided. A laser beam LB generated from a laser light source (not shown) and passed through an expander (not shown), a cylindrical lens, or the like is light having a wavelength that does not expose the photoresist, and is incident on the beam splitter 30 and split into two light beams. Is done. One of the laser beams is reflected by the mirror 31, passes through the beam splitter 32, and is converged by the imaging lens group 33 so that the cross section becomes a band-shaped spot light. In the meantime, the light enters the first folding mirror 34 arranged so as not to shield the projection optical path of the circuit pattern image.
The first turning mirror 34 reflects the laser beam upward toward the reticle R. The laser beam is provided below the reticle R, enters a mirror 35 having a reflection plane parallel to the surface of the reticle R, and is reflected toward the center of the entrance pupil Ep of the projection lens 1. The laser beam from the mirror 35 is converged by the projection lens 1 so that the principal ray is perpendicular to the wafer WA, and is imaged on the wafer WA as a strip-shaped spot light LYS elongated in the X direction. The spot light LYS is a diffraction grating mark My (No.
(See the figure) is relatively scanned in the Y direction to detect the position of the mark. When the spot light LYS irradiates the mark, diffracted light is generated from the mark. The light information returns to the projection lens 1, the mirror 35, the mirror 34, the imaging lens group 33, and the beam splitter 34 again, is reflected by the beam splitter 34, and is focused on the condenser lens and the pupil of the projection lens 1.
The light enters an optical element 36 composed of a spatial filter conjugate with Ep. The optical element 36 transmits diffracted light (first-order diffracted light or second-order diffracted light) from the mark, blocks specularly reflected light (zero-order light), and receives the diffracted light via a mirror 37 at a photoelectric element 38. Focus on the surface. The photoelectric element 38 outputs a photoelectric signal according to the amount of the collected diffracted light. As described above, the mirror 31, the beam splitter 32, the imaging lens group 33, the mirrors 34 and 35, the optical element 3
The mirror 37, the photoelectric element 38, and the mirror 37 constitute a through-the-lens type alignment optical system (hereinafter, referred to as a Y-LSA system) for detecting the position of the mark on the wafer WA in the Y direction.

On the other hand, another laser beam split by the beam splitter 30 is a through-the-lens type alignment optical system (hereinafter, referred to as X-LSA) for detecting the position in the X direction of the mark Mx (see FIG. ). X-LSA system is Y
-Mirror 41, beam splitter 42, just like LSA system
Imaging lens group 43, mirrors 44, 45, optical element 46, mirror 4
7, and a strip-shaped spot light LXS elongated in the Y direction and formed on the wafer WA.

The main controller 50 controls the photoelectric signals from the photoelectric elements 38 and 48, the WGA
Alignment signals from 20,21 and laser interferometer 9,10
And performs various arithmetic processing for position adjustment, and outputs a command for driving the motors 4, 5, and 6. The main controller 50 includes an arithmetic processing unit such as a microcomputer or a minicomputer. The arithmetic processing unit includes design position information of a plurality of chips CP formed on the wafer WA (chip arrangement coordinate values on the wafer WA). Etc.) are stored.

Now, FIG. 3 is a diagram showing another configuration provided in the apparatus of FIG. 2, a fly eye lens FL, the beam splitter BM _1, the mirror M _1, the condenser lens CL, and although illustration is omitted reticle An illumination optical system for exposure is constituted by an image forming optical system ILS of a blind (illumination field stop) and the like.
Secondary light sources on the emission side of the fly-eye lens FL are broken lines (principal rays) l ₁ and l ₂ passing through both ends of the pattern area PA of the reticle R.
As is clear from FIG. 7, an image is formed on the pupil Ep. At two or three positions outside the circuit pattern area PA of the reticle R,
Marks for reticle alignment is formed, Each of the reticle mark, the beam splitter BM _2, the objective lens OB _1, beam splitter BM _3, BM _4, and detected by the detection system RCV through an imaging lens G ₁ Is done. FIG. 3 shows only one reticle alignment system on reticle R in detail, and the configuration is the same for reticle alignment systems disposed at other positions. An index mark or a fixed slit is arranged in the detection system RCV, and the detection system RCV detects a position shift between the reticle mark and the fixed slit, and moves the reticle stage RST so that the shift is equal to or less than an allowable value. Wiggle. When detecting a reticle mark, an optical
The illumination light of the exposure wavelength guided through the fiber FB ₁ is
Lens system G _3, field stop Ap, and through the lens system G ₂ is incident on the beam splitter BM _3, to the coaxial incident illumination to the reticle mark through the objective lens OB _1. Field stop Ap has become a reticle R is conjugate with the objective lens OB ₁ and the lens system G _2, only the desired mark region including the reticle mark is irradiated. On the other hand, on the wafer stage 3, a reference mark plate FM having a surface coated with reflective chrome and having an alignment mark (reference mark) formed on a part thereof is fixedly provided. At the time of reticle alignment, the stage 3 is positioned such that the unmarked surface portion of the reference mark plate FM is located at the projection position of the mark area of the reticle R. The mark on the wafer WA is placed on the surface of this reference mark plate FM.
A mark having the same shape as Mx, My is formed, and this mark is detected by a Y-LSA system (or an X-LSA system) including mirrors 34, 35 and the like. Furthermore the reference mark plate FM on the surface is formed a transparent portion removing the chromium layer in a slit shape, the illumination light of the exposure wavelength is irradiated from the back side through the Optical fiber FB _2. As a result, a light emitting slit mark is formed on the image forming plane of the projection lens 1 (a conjugate plane with the reticle).
Back projected to form an image on the reticle mark. The image light beam of the luminescent mark is reflected by the beam splitter BM ₂ and passes through the objective lens OB ₁ and the beam splitter BM ₄ to the photoelectric detector DT.
Received at ₁ The light receiving surface of the detector DT ₁ is the pupil of the projection lens 1
It is arranged almost conjugate with Ep. Also, this detector DT ₁
When is not used, of the image rays of the light-emitting mark, the light flux that passes through the beam splitter BM ₂ and travels back to the illumination optical system for exposure is reflected by the beam splitter BM ₁ and is reflected by the photoelectric detector DT ₀ . Receive light. This detector DT _{0 is} also the pupil Ep of the projection lens 1
And conjugated.

The above-mentioned detectors DT ₀ and DT ₁ (either one may be sufficient) are:
It is used to measure the relative positional relationship between the spot light LYS and LXS of the Y-LSA system and the X-LSA system after reticle alignment using the detection system RCV. The signal processing of the detector DT ₀ or DT ₁ is performed in the same manner as the signal processing system of the photoelectric elements 38 and 48 shown in FIG.
The signal waveform level is digitally sampled in response to a pulse (every 0.02 μm), sequentially stored in a memory, and then subjected to waveform analysis.

FIG. 4 shows the respective spot lights θSP, YSP, Y-LSA of the WGAs 20 and 21.
System, X-LSA spot light LYS, LXS, reticle mark,
FIG. 3 is a layout diagram showing the relationship between various marks on a reference mark plate FM on an image forming plane of the projection lens 1 (the surface of the wafer WA). In FIG. 4, when a coordinate system xy having the optical axis AX as the origin is defined, the x-axis and the y-axis respectively represent the moving direction of the stage 3, that is, the length measuring axes of the laser interferometers 9 and 10. In Fig. 4, the optical axis AX
Is the image field if of the projection lens 1, and the inner rectangular area is the projection image Pr of the pattern area PA of the reticle R. The spot light LYS is formed at a position outside the projection image Pr in the image field if and coincides with the x axis, and the spot light LXS is also formed at a position outside the projection image Pr within the image field if, along the y axis. It is formed to coincide with the above. On the other hand, the two spot beams? SP, so that the vibration center of the YSP coincides on line (x-axis parallel to) l ₃ at a distance Y ₀ in the y direction from the x axis, and distance Dx of the x-direction It is determined to be smaller than the diameter of the wafer WA. In this device, the spot light θSP, Y
The SPs are arranged symmetrically with respect to the y axis, and the main controller 50 stores information on the positions of the spot lights θSP and YSP with respect to the projection point of the optical axis AX. The main controller 50 also
Information about the center position (distance X1) of the spot light LYS in the x direction with respect to the projection point of the optical axis AX and the center position (distance Y1) of the spot light LXS in the y direction are also stored.

Furthermore, reticle mark RMx,
RMy, RMθ are provided, the mark RMx is a slit pattern parallel to the y-axis, and the marks RMy, RMθ are slit patterns parallel to the x-axis. When the reticle alignment is precisely achieved, the mark RMx coincides with the y-axis, and the marks RMy and RMθ both coincide with the x-axis.

On the other hand, as shown in FIG. 4, the reference mark plate FM has, as an example, a light emitting slit ISy parallel to the x axis, a light emitting slit ISx parallel to the y axis, and a spot light YSP extending parallel to the x axis.
Diffraction grating mark FGy detectable by θSP, LYS,
And a diffraction grating mark FGx that can be detected by the spot light LXS. And here, the emission slit ISx and the mark FGx are arranged on a line parallel to the y-axis,
The emission slit ISy and the mark FGy are arranged on a line parallel to the x-axis. In the case of this embodiment, the marks Mx and My provided for each chip pattern on the wafer WA have the same shape as the reference marks FGx and FGy, and are not related to the reticle R.
Detected by the SA system. Then, the stage 3 is moved so that the emission slit ISx coincides with the reticle mark RMx, and the position Xbr of the stage 3 in the x direction at that time is obtained by the laser interferometer 10, and then the reference mark FGx is set to the X-LSA spot light. The stage 3 is moved so as to be detected by the LXS, and the position Xbs in the x direction when the spot light LXS and the mark FGx match is obtained. The main control system 50 has the position Xbr and the position Xbs
Is calculated and stored. Similarly, the emission slit
The position Ybr in the y direction when ISy and the reticle mark RMy (or RMθ) match, and the position Ybs in the y direction when the Y-LSA spot light LYS and the reference mark FGy match are obtained. The difference ΔYb is stored. These two values, ΔXb,
ΔYb is the intersection of the extension of the spot light LXS, LYS and the mark R
This is a slight relative displacement (baseline amount) between mx and the intersection (reticle center point) of the extension of the mark RMy (RMθ), and is important data in the subsequent wafer alignment. That is, a pattern obtained by uniformly adding the correction values of ΔXb and ΔYb to the position measurement values of the marks Mx and My on the wafer WA detected by the X-LSA system and the Y-LSA system is used as the pattern of the reticle R. Chip pattern Cp based on the center point of area PA
Is detected as the coordinate position of. In this manner, even if the setting accuracy of the reticle alignment in the x and y directions is insufficient, the position of the center point of each chip pattern can always be specified with reference to the reticle center point.

Next, the alignment method according to the present invention using this apparatus will be described together with the operation of the apparatus with reference to the flowchart of FIG. Note that this alignment is performed for the second and subsequent layers of the wafer WA, and the chip pattern Cp and the alignment marks Mx and My have already been formed on the wafer WA.

Steps 100 to 104 in FIG. 1 are exactly the same processing as described in Japanese Patent Application Laid-Open No. 61-44429. That is, in step 100, the orientation of the wafer WA
Preliminary positioning of wafer WA on pre-alignment station based on flat and wafer outline,
Thereafter, in step 101, the wafer WA is transferred from the pre-alignment station to a holder on the wafer stage 3 and fixed by suction. Next, in step 102, two Ws
Using the GA systems 20 and 21, two global marks GY and Gθ on the wafer WA are simultaneously detected as shown in FIG.
The wafer holder is slightly rotated so that the center of vibration of the spot light YSP in the y direction coincides with the center of the mark GY, and the center of vibration of the spot light θSP of the WGA 20 in the y direction coincides with the center of the mark Gθ. With this operation, the relative rotation error between the arrangement coordinate system of the chip patterns on the wafer WA and the xy coordinate system of the wafer stage 3 is suppressed to an allowable value or less. Although this value is very small, there may still be strictly residual rotation errors. The global marks GY and Gθ on the wafer WA are formed at intervals Dx in a street line passing near the center of the wafer and parallel to the x-axis. Although the chip pattern is omitted in FIG. 5, the mark G
Y, Gθ are in the form of a diffraction grating similar to the marks Mx, My for each chip pattern, are elongated in the direction of the street line, and are made longer (about twice) than the marks Mx, My.

Through the above step 102, the global alignment (the y direction and the θ direction) of the wafer WA is completed, and then the EGA method is executed in the order of steps 103 and 104. In step 103, as shown in FIG. 12 (B), the position coordinates of each mark Mx, My of the specified plurality of chip patterns are represented by X-L
The measurement is performed by the SA system, the Y-LSA system, and the laser interferometers 9 and 10. Then, the previously stored baseline amount ΔX
The measured values corrected by the values of b and ΔYb are stored as actually measured coordinate values. In step 103, if the detection is inconvenient or the reliability of the measurement is obviously lost, the actually measured value of the measurement mark (chip pattern) is not used in subsequent calculations. Alternatively, when a part of the mark Mx, My of the specified chip pattern is damaged and the waveform of the photoelectric signal is clearly determined to be abnormal, the sample pattern is replaced with a chip pattern adjacent to the specified chip pattern. Alignment may be used. As described above, marks for at least three chip patterns
When the actually measured coordinate values of Mx and My are obtained, in the next step 104, a linear error parameter is determined by the least square method using the design coordinate values and the actually measured values. The determination method is the same as that disclosed in JP-A-61-44429. Therefore, in step 104, the linear error parameters α,
β, θ, ω, Ox, Oy are determined.

Here, α: linear expansion / contraction ratio of wafer in x direction β: linear expansion / contraction ratio of wafer in y direction ω: orthogonality error amount of coordinate system xy θ: residual rotation error amount of chip array coordinate system with respect to coordinate system xy Ox: wafer Oy: Offset of wafer in the y direction (μm) (Dxn, Dyn) is the design coordinate value of the n-th chip pattern.

(Fxn, Fyn) is the predicted coordinate value of the n-th chip pattern in consideration of the linear error parameter.

The above error parameters are obtained by approximation assuming that both the orthogonality error amount ω and the remaining rotation error amount θ are small. The method of obtaining each parameter is described in Japanese Unexamined Patent Publication No. It is also disclosed in Japanese Patent No. 84516.

In the matrix of the linear error parameters in the equation (1), α, β, Ox, and Oy are independently obtained in the calculation process.
θ and ω cannot be obtained as they are,
It can be obtained in the form of θ, −α (θ + ω).

In the case of the EGA method, there are four error parameters required in the result, α, β, β · θ, and −α (θ + ω). Not something.

Next, steps 105 and 106 are executed.
The data required in 5,106 needs to be acquired in advance in another sequence or the like. The sequence will be described later in detail.

In step 105, the standard deviations σ _ux and σ _uy of random position errors of the actual chip pattern are _provided to the main controller 50 as data with _respect to the position where the chip pattern is regarded as a linear array. If the layer formed on the wafer WA is the first-layer chip pattern arrangement, the statistics (σ _ux , σ _uy ) can be grasped from the positioning characteristics of the wafer stage. Also, when the layer on the wafer WA is burned while moving the wafer stage based on the linear arrangement pitch of the chip pattern even after the second layer (EGA
Method, etc.), the statistics (σ _ux , σ _uy ) can be _similarly grasped from the positioning characteristics of the stage. Furthermore, for a layer baked by the ESA method or the D / DA method, a pilot wafer having the layer is flowed, overlay exposure is performed by the EGA method, and the statistics are obtained from the overlay result of the chip pattern. (Σ _ux , σ _uy ) can be obtained. It is also possible to accumulate data for layers having different baking conditions and use the data later as empirical data.

Here, the concept of the standard deviations σ _ux and σ _uy of random position errors of the chip pattern will be described with reference to FIG. In FIG. 6, lines Lx ₁ and Lx ₂ parallel to the x-axis and lines Ly ₁ , Ly ₂ , Ly ₃ , Ly ₄ and Ly ₅ parallel to the y-axis are each a chip pattern specified by the EGA method. In the ideal case where there is no random array position error, all the centers CC of the chip patterns Cp are aligned with the respective intersections of the lines. In the case of FIG. 6, the chip pattern arrangement is shifted by a certain amount in the x and y directions with respect to the reference lattice as a whole, but this is exaggerated for easy understanding of the illustration. It is a very small amount of 1 μm or less. First, deviation amounts ΔXi and ΔYi in the x and y directions between the reference grid intersection and the chip center CC are determined for each chip pattern. It is better to increase the number m of chip patterns to be measured, and here it is assumed that there is no random measurement error at the time of measurement. next,
The average value Kx, Ky of the m pieces of shift amount data is obtained by the following equation.

Then, the standard deviations σ _ux and σ _uy in the x and y directions are _obtained by the following equations.

The above is an example of a method of obtaining a statistic relating to a random position error. In actuality, as described above, there are three cases, namely, condition A: a layer of a chip pattern on a wafer to be overlaid and exposed. Is formed by the first print (first layer), Condition B: When the chip pattern layer on the wafer to be overlap-exposed is formed by EGA method, Condition C: Wafer to be overlap-exposed When the upper chip pattern layer is formed by the ESA method or the D / DA method, the statistics (σ _ux , σ _uy ) are determined in advance by the optimal method according to
And the numerical value may be different.

In the next step 106, the mark M of the chip pattern
The main controller 50 _uses the standard deviations σ _ux , σ _uy of random measurement errors included in the measured values when x and My are measured as data.
Give to.

This depends on the distortion of the mark shape, the optical characteristics of the resist layer on the wafer surface, or the noise present in the measurement form, etc., using a pilot wafer to perform overlay exposure using the ESA method or D / DA method, Superimposition result (misalignment) of chip patterns formed on the wafer,
Alternatively, the statistics (σ _wx , σ _wy ) can be obtained from the positioning characteristics of the stage previously given as data. In addition, the chip position coordinates (actually measured values) obtained by performing the mark detection of a plurality of chip patterns in step 104, and the chip position predicted coordinate values calculated from the equation (1) using the linear error parameters determined there. (Fxn, Fy
n) and the statistic σ _u given in step 105. As in the case of the statistic σ _u , it is also possible to determine an empirically optimum value by accumulating data corresponding to the layer. In addition, signal waveform distortion at the time of mark detection may be considered as a random measurement error.

FIG. 7 shows an example of a state of relative scanning between the mark Mx and the spot light LXS and a state of a waveform of a photoelectric signal. As shown in FIG. 7A, the mark Mx has a diffraction grating shape having a constant pitch in the y direction orthogonal to the relative scanning direction (X direction).
Are scanned in parallel. At this time, the photoelectric element 48
Is obtained as shown in FIG. 7 (B). This signal waveform is usually compared with a certain slice level Vr, and the center point of each intersection of the rising and falling slice levels Vr of the signal waveform is determined as the center position of the mark Mx in the x direction. The signal waveform of FIG. 7 is a case where the symmetry is preserved, but due to the distortion of the mark shape, even a mark having the same pitch configuration becomes an asymmetric waveform as shown in FIG. 7 (C). In addition, a clear peak cannot be obtained as shown in FIG. 7 (D), or a peak which is originally a single peak causes a mountain crack as shown in FIG. 7 (E). In the case of the waveform as shown in FIG. 7 (D), it is determined by the waveform analysis algorithm that the mark position detection is inappropriate,
Can be rejected in advance. In the case of a mountain crack waveform, although depending on the degree, when two adjacent peaks generated by the mountain crack are within a certain interval determined by the mark width, it is regarded as one mark waveform, and the mark center position is determined by setting the slice level. Can be measured. However, as in the case of the waveform of FIG. 7 (C), a random measurement error is included to a degree that cannot be ignored.

It is also known that random measurement errors vary depending on the mark position on the wafer. This is because the influence of the wafer process (thermal or chemical treatment), the influence of the resist layer, and the like slightly differ depending on the position on the wafer.

In the next step 107, the error parameters (α, β, θ,
ω, Ox, Oy), the coordinate position (Fxn, Fyn) of the chip pattern calculated by the EGA method, and the standard deviation (σ _ux , σ _uy ) and a standard deviation (σ _wx , σ _wy ) of a random measurement error as the second statistic are created as a position estimation filter (arithmetic expression). This position estimation filter takes in input information that can change over time in time series, reduces random errors included in the input information, and obtains output information estimated to be closer to the actual change. The Kalman filter is improved for alignment, and is used to obtain a least-squares estimation amount of a chip position. As described above from the conclusion, this position estimation filter uses the ESA method (or D / DA method) when the statistical error (σ _wx , σ _wy ) of the measurement error that occurs during mark detection among random error factors becomes large. ), The weight is placed on the alignment result by the EGA method rather than the alignment result by the EGA method. When the statistical value (σ _ux , σ _uy ) of the random position error of the chip pattern arrangement becomes larger, It works to put weight on the alignment result of ESA method (or D / DA method).

Therefore, when the position estimation filter of the present embodiment is used, the mark Mx, My is measured and aligned for each chip pattern on the wafer WA after the measurement operation by the EGA method.
It is assumed that the ESA (or D / DA) method is executed.

Therefore, first, a method of determining a position estimation filter will be described. Before that, a general least squares estimation rule will be described.

Now, the physical quantity to be measured is represented by x, and it is called a signal (input information). If the signal fluctuates randomly, it is considered as one random variable. If the signal consists of a number of physical quantities x ₁ , x ₂ ... X _n , it is represented as a random variable vector as follows:

Further, the measured value for the physical quantity y _1, y ₂ ...... y _m and a plurality obtained, if the noise included in each measurement value is _{w 1, w 2 ...... w m} , measured amount and noise following It is represented as

signal Is not directly obtained, but its estimate Is the measured value shown below Is given by a linear operation expression of

Is defined as

This error vector Is zero, and any 2
Least-squares estimator with estimation rule that minimizes the following form And is defined by the following equation.

However, In equations (9) and (10), Represents the transpose of Represents the inverse matrix of.

As described above, equations (9) and (10) express the concept of the general least-squares estimation rule. Next, a case where this is applied to a position estimation filter used for alignment of a chip pattern on a wafer will be described. explain. Signals handled by general formula Is the true coordinate value of the chip pattern on the wafer And the true coordinate value of the n-th chip pattern Is represented by the following equation.

However, Therefore, if equation (11) is rewritten in the same manner as equation (1), equation (12) is obtained.

here Is a two-dimensional random variable vector corresponding to a random position error component of the chip pattern, and is handled as follows.

Here, u _{x is} a random arrangement error in the x-axis direction of the chip pattern.

u _y : random array error of the chip pattern in the y-axis direction.

It is.

Furthermore, a vector of random error components The average of Is defined as follows:

On the other hand, the measured value of the chip position obtained by detecting the mark of the n-th chip pattern on the wafer Can be defined as follows with respect to the above equation (5).

here Is a two-dimensional random variable vector corresponding to observation noise, that is, a random measurement error component at the time of mark position measurement, and is handled as follows.

Here, w _{x is} a random error in the x-axis direction at the time of mark measurement, and w _{y is} a random error in the y-axis direction at the time of mark measurement.

Based on the above correspondence function, the operation expression of the position estimation filter is determined as follows in the same manner as Expression (9). Here, in equation (9) The estimated coordinate value (least squares estimator) as an output value corresponding to (Txn, Tyn), and in equation (9) To Is equivalent to

Also, from equation (10) above, Becomes

Therefore, the following expression for the position estimation filter is derived from Expression (19).

Which are known because they are provided as data.

Here, the following approximation can be assumed for the linear error parameter relating to the chip arrangement of the wafer.

θ≪1, ω≪1, α ≒ 1, β ≒ 1 On the other hand, true signal In equation (11), Is a random variable vector and the other Is a coefficient vector, so the vector In Equation (6) It is determined by making it correspond to.

Therefore, Also, the predicted coordinate values calculated by the EGA method Is the equation (9) , And has already been determined by equation (1), so the right side of equation (21) is All variables except are represented by known data or calculated values. Therefore, a specific position estimation filter using the law of least squares estimation is given by the following equation.

This gives the measured value Is given, it becomes possible to calculate the estimated coordinate values (Txn, Tyn) through the chip position estimation filter.

In this equation (25), the measured value (Gxn, Gyn) is an actual measured chip position obtained by detecting the marks Mx, My of the individual chip patterns in the subsequent processing.

Equation (25) can be expressed in vector notation as equation (26), Is the inverse of.

In this equation (26), Is a value (variance matrix) related to the statistics of random array position errors, Is the value related to the statistical value of the random measurement error (variance matrix)
It is. Further, the coefficient term of the linear error parameter in the equation (1) is Offset (Ox, Oy) Then, the following vector expression is obtained.

However, As described above, when the position estimation filter is determined, step 108 in FIG. 1 is executed next. In step 108, position measurement is performed using the marks Mx and My of the individual chip patterns, and the obtained actually measured coordinate values (Gxn, Gyn) are calculated by the equation (2).
5), the corresponding predicted coordinate values (Fxn, Fyn) obtained from Expression (1) are substituted into Expression (25) to obtain estimated coordinate values (Txn, Tyn), and this value is used. Stage 3
Is aligned with the reference position (the center point of the reticle).

In step 109, exposure is performed on the aligned chip pattern. Then, in step 110, the wafer WA
When it is determined that the exposure of all the above chips has been completed, the wafer WA is unloaded in the next step 111, and the exposure processing of one wafer is all completed.

The operation of the present embodiment has been described above. The flowchart of FIG. 1 will be described in further detail with reference to FIG. The block in FIG. 8 is constituted by software of a computer provided in the main controller 50 in FIG. 2, or a database (memory). Block 200 is the data of the design position coordinates of the chip pattern on the wafer WA (Dxn, Dyn) is stored. Block 201 is a chip selector for selecting a chip for performing mark detection (position measurement) among chip patterns on the wafer WA.
Designation of sample alignment chip for method A, or
Specify the alignment chip by ESA method (or D / DA method).

A block 202 is a measuring unit for measuring the position of the chip pattern designated by the chip selector 201 using an alignment sensor such as an X-LSA system or a Y-LSA system. The interferometer 9 shown in FIG. , Based on measurements 205 from 10,
The actual coordinate position of each chip pattern is output. This output value is supplied to the linear error parameter of the block 203 via the switch Sw during the sample alignment of the EGA method. Is sent to the decision unit. Block 204 is a parameter Is an EGA operation unit using Equation (27), that is, Equation (1) is calculated based on (Fxn, Fyn) is output. A block 207 is an operation unit of the position estimation filter defined by the equation (25) or (26), and is a first statistic regarding a random arrangement error obtained in advance. That is, the second statistic about the standard deviation (σ _ux , σ _uy ) and the random measurement error That is, the standard deviations (σ _wx , σ _wy ) and the
From the storage unit, and the coefficient matrix part in the equation (26), Is calculated in advance and converted into a constant.

Measurement values to be input to position estimation filter after sample alignment by EGA method is completed When all the other data are determined, the switch Sw is switched in the direction shown in the figure, and the chip selector 201 designates an alignment chip by the ESA method (or the D / DA method). Then, according to the interferometer measurement value 205, the first (n =
The control unit 206 of the stage 3 is controlled so that the chip position of 1) is measured by the X-LSA system and the Y-LSA system. The position measurement value output from the measurement unit 202 is the actually measured coordinate value. (Gxn, Gyn) is sent to the block 207, and from the block 204 at the same time, the predicted coordinate value of the corresponding chip pattern (Fxn, Fyn) is also sent. These two coordinate values Based on the position estimation filter estimates the coordinate values (Txn, Tyn) is calculated and output to the algorithm selector in block 210. The algorithm selector 210 is unnecessary when positioning the stage 3 using only the estimated coordinate values (Txn, Tyn). However, the stepper uses the actually measured coordinate values (Gxn, Gyn) and the predicted coordinate values (Fxn, Fyn). Since the positioning mode of the stage 3 is also required, the three coordinate values are selectively switched and output to the stage controller 206.

The controller unit 206 outputs the coordinate values output from the selector 210. Is set as a target value, and the stage 3 is servo-controlled so that the target value and the interferometer measurement value match with high accuracy.

In the above description, equation (25) of the position estimation filter can be modified to a simpler equation.

Therefore, And expressing equation (25) for each x, y component, Becomes

here, Then, these coefficients (Qx, Qy) are calculated in advance in the block 207 and stored as constants, and the equation of the position estimation filter can be modified as follows.

The constants (Qx, Qy) are weighted according to the magnitude relationship between the random array position error and the random measurement error, or are weighted to the actually measured coordinate values (Gxn, Gyn) of each chip pattern, or are predicted by the EGA method. This corresponds to a weight coefficient for determining whether to give a weight to the predicted coordinate value (Fxn, Fyn) of the chip pattern.

The coefficient (Qx, Qy) takes a value smaller than 1, and the statistic of the random position error (σ _ux , σ _uy ) is relative to the statistic of the random measurement error (σ _wx , σ _wy ). , The coefficient (Qx, Qy) approaches 1, and the statistic (σ _wx , σ _wy ) is relatively larger than the statistic (σ _ux , σ _uy ). At times, the coefficients (Qx, Qy) approach zero. As is clear from equation (30), the coefficients (Qx, Q
If y) becomes smaller than 1 and approaches 0 as much as possible, the equation (3)
The two items on the right side of (0) are ignored, and Txn = Fxn and Tyn = Fyn are calculated. Also, if the coefficients (Qx, Qy) approach 1 as much as possible, the right side of equation (30) Are ignored, and Txn = Gxn and Tyn = Gyn are calculated.

As described above, in the position estimation filter of the present embodiment, the chip pattern is assigned to any coordinate value between the predicted coordinate value (Fxn, Fyn) and the measured coordinate value (Gxn, Gyn) determined by the EGA method. It will be positioned.

FIG. 9 shows the deviation σ of the alignment error when the standard deviation σ _w of the random measurement error is changed while the standard deviation σ _u of the random array position error is fixed at a certain value.
₇ is a graph in which _e is obtained by simulation. Ninth
In the figure, the horizontal axis represents the deviation σ _w (μ
m), and the vertical axis represents the deviation σ _e (μm) of the alignment error.
Represents When the deviation σ _u of the random position error is constant, the deviation characteristic of the positioning error when the overlay exposure is performed by the EGA method is constant irrespective of the random measurement error as in CV2.

In addition, the deviation characteristic of the alignment error when the overlay exposure is performed by the ESA (or D / DA) method is CV1, and the deviation σ _{w of the} random measurement error is almost independent of the deviation σ _u of the random position error like CV1. Increase in proportion to On the other hand, the deviation characteristic of the registration error at the time of performing the overlay exposure using the estimated coordinate values (Txn, Tyn) determined through the position estimation filter according to the present embodiment is like CV3.

Characteristics CV3 is, sigma _w is time smaller than the intersection Cr characteristics CV1 and CV2 is asymptotic to the linear characteristics CV1, sigma _w is time greater than the intersection Cr becomes hyperbolic shape as gradually approaches a straight line characteristic CV2 , Which is smoothed to the better one of the two characteristics CV1 and CV2, and the accuracy is improved as compared with either case.

The part where the effect of improving the accuracy can be expected most is the intersection Cr.

Note that the change in the deviation σ _u of the random position error depends on the characteristic CV
2 means translate up and down on the graph,
Even in that case, the characteristic CV3 is always below the characteristics CV1 and CV2.

FIG. 10 is a diagram showing an example of this, in which chips C3... C5... C8 are exposed in the order of chips C3... C5. Exposure by the ESA method is performed.

First, several chips near the chip C1, for example, chips Ca, Cb,
Perform sample alignment (obtain measured coordinate values) for Cc and C3, and then perform alignment for chip C1 to obtain measured coordinate values. As described above, as the exposure by the ESA method progresses, the measured coordinate values of the exposed chip Data is accumulated, the error parameters determined by the EGA method first As appropriate. For example, when aligning chips C5 and C10, if nonlinear elements are included in the chip arrangement, the parameters initially determined using chips Ca, Cb, Cc, C1, and C3 In some cases, optimum accuracy cannot be obtained. Therefore, already measured coordinate values Error parameters using chips C3, C5, Cc, C6, etc. As a modified example, first, similarly to the EGA method, the wafer WA is divided into appropriate blocks, and representative chips Cc, Cd, Ce, and Cf are selected from each block, and the respective measured coordinate values are selected. Is obtained in advance by sample alignment,
In addition, sample alignment is performed for nearby chips Ca and Cb before exposure to the ESA method, and when exposure of chip C1 is performed, measured coordinate values of chip C1 are used. Is obtained, a chip close to the chip C1 (for example, C1, Ca, C
The weight is increased for the measured coordinate values of (b, Cc), and the measured coordinate values of chips (eg, Ce, Cf) far from chip C1 , The weight is reduced, and then the error parameter Is calculated. Then, as the exposure progresses, the error parameter determined by increasing the weight for the actually measured coordinate values of several chips near the chip to be exposed is determined. To be corrected. In this way, the EGA optimized for each block on the wafer containing the chip to be exposed
Since the method can be applied, the influence of the nonlinear element can be further reduced.

It should be noted that the method shown in FIG.
This method is the same as the method disclosed in Japanese Patent Application Laid-Open No. 1133, and when an arithmetic expression of the EGA method is used, it is also called a variable block EGA method.

Next, another alignment sensor that can be used in the alignment method according to the embodiment of the present invention will be briefly described. One of the alignment sensors is a wafer mark image observation type alignment system (referred to as FIA) with an image processing function provided separately from the projection lens, similar to WGA20 and WGA21.
The other is a TTR alignment system (D / D. Alignment system) for directly detecting a positional shift between a reticle mark and a wafer mark via a projection lens.

The FIA system irradiates the mark area on the wafer with broadband illumination light, which is insensitive to the resist layer on the wafer and has a wavelength bandwidth of about 300 nm, through the achromatic objective lens, and reflects the reflected image to the objective lens. Is formed on the two-dimensional image pickup device via the. An image signal corresponding to the contrast of the captured mark is processed by a high-speed processor for image processing, and the center point of the mark is obtained as an image position in the screen. Further, after the shift of the mark center point with respect to the cursor line set in advance on the screen is determined by the number of pixels, the shift is converted into the shift amount in the coordinate system of the stage 3. The amount of this displacement is determined by the current stop position of stage 3 (interferometer 9,
Corrected from 10 readings), the measured coordinate value of the mark center point become. When using this FIA system, the X-LSA system, Y-LS
Since the alignment is site-by-site as in the case of the A system, using the fiducial mark plate FM on the stage 3,
Distance between the center point of the reticle pattern area and the cursor line serving as a reference index in the FIA system (baseline ΔXbr, Δ
Information about Ybr) is accurately measured in advance. And the measured coordinate values Either the base line (ΔXbr, ΔYbr) is used for the EGA method calculation or position estimation filter calculation, or the offset after the calculation If the base line is uniformly added to the coordinates, the coordinates can be converted to the position coordinates of the superposition.

Using such an off-axis FIA system,
There is no problem in performing sample alignment for the EGA method, but there is a problem that measuring the coordinate positions of all chip patterns on a wafer is extremely disadvantageous in terms of throughput. Therefore, measured coordinate values for all chips on wafer WA Without thinning, sample alignment is performed. For example, before the exposure operation, every two chips in the x and y directions of the chip arrangement on the wafer are FI
Measured coordinate value of chip pattern using A system Ask for. Then, using the coordinate values of three or more chip patterns from the result, the error parameters of the EGA method Is calculated and the predicted coordinate value Is required.

At the time of exposure operation, if the chip pattern to be exposed has been sample-aligned in advance, its measured coordinate values And predicted coordinate values And the estimated coordinates using Ask for. When the chip pattern to be exposed is not sample-aligned in advance, the x direction, the y direction,
Alternatively, the estimated coordinate value can be obtained by using the actually measured coordinate value of the chip pattern adjacent in any of the oblique directions and the predicted coordinate value of the chip pattern to be exposed.

If the thinning is performed as described above, only about 1/9 of the number of chips on the wafer needs to be sample-aligned before the exposure operation, and a decrease in throughput can be suppressed to a small extent. The method of thinning may be every other in the x and y directions of the chip arrangement, or the number of thinning may be changed in the x and y directions.

On the other hand, various types of TTR alignment systems have been proposed and put into practical use. However, an interference alignment method has attracted attention because it can detect positional deviation with higher resolution (on the order of nm).

The interference alignment method is described in, for example, JP-A-63-283129.
As disclosed in Japanese Unexamined Patent Publication, a diffraction grating measured in the pitch direction is provided for each of the chip patterns on the wafer, and a similar diffraction grating is provided at a corresponding position on the reticle. Irradiate coherent beams having different frequencies from two directions so as to have a predetermined crossing angle, and diffracted light reflected from the reticle diffraction grating and interference beat light reflected from the wafer diffraction grating. This is a method (heterodyne method) in which the relative phase difference between the diffracted light returning via the projection lens and the transparent portion of the reticle and the interference beat light is detected as a positional shift between the reticle and the wafer (chip pattern). In this case, ± 180 ° of the relative phase difference corresponds to ± 1/4 of the grating pitch, and if the pitch of the wafer grating is 4 μm (line and space of 2 μm) and the phase detection resolution is 1 °, the diffraction grating Is 4 × 1/4 × 1/180 ≒ 5.5 nm. Using such a TTR alignment system, the measured coordinate values of the mark (diffraction grating) attached to each of the chip patterns on the wafer Is directly measured with reference to the mark (diffraction grating) on the reticle. Furthermore, if the mark on the reticle and the mark of the chip pattern on the wafer are formed in the area corresponding to the scribe line, the D / DA method that completely matches the alignment position and the exposure position can be realized. Unlike the site-by-site method, there is no need to measure and manage the baseline amount using the fiducial mark plate FM.

When using this TTR alignment system, it is necessary to precisely drive reticle positioning to zero, especially for rotation.

Then, sample alignment is performed on some chip patterns on the wafer based on the marks on the reticle. At this time, assuming that the normal wafer global alignment has been completed, the chip to be sample-aligned on the wafer is a reticle with an accuracy of ± 1 μm or less according to the readings of the stage 3 and the interferometers 9 and 10. It is positioned at the projection point of the pattern. Then, while the stage 3 is stopped, the deviation amount of the wafer lattice with respect to the reticle lattice is obtained from the relative phase difference by the TTR alignment system, and the actually measured coordinate value of the chip is obtained based on the deviation amount and the current stop position of the stage 3. calculate. After sample alignment for several chips, EGA
Error parameter by the formula After calculating, the exposure sequence by the D / DA method is started.
The subsequent sequence is the same as in the previous embodiment, and the measured coordinate value of the grid mark is , And the estimated coordinate value through the position estimation filter Should be obtained. As described above, in the D / DA method using the TTR alignment system, a random measurement error is likely to occur when the measurement value is used as it is, and a random overlay error is likely to occur for each chip on the wafer. However, by passing the measured values through a position estimation filter made by applying the least squares estimation rule, the random component is smoothed, and the effect of reducing the random overlay error in all chips on the wafer is obtained.

60, the embodiment of the present invention, it is necessary to and a standard deviation sigma _u random sequence error, both the standard deviation sigma _w random measurement error determined in advance. Random arrangement errors were first considered under three conditions A, B, and C. Therefore, the deviation σ _u based on these three conditions A, B, C
A brief description of how to determine is given.

Condition A is when the chip pattern on the wafer is the first layer, and the cause of the random arrangement error in the first layer (first print) is only the positioning characteristics of the stage 3. Condition B is the case where the chip pattern on the wafer is the second and subsequent layers, and the layer is exposed by the EGA method. It is a characteristic. Therefore, it is necessary to separately examine the positioning characteristics of the stage alone.
The positioning characteristics of the stage can be measured, for example, by developing a step-exposed wafer using a test reticle having a vernier mark and then measuring the deviation of the resist image of the vernier mark with a dedicated measuring instrument, or using a vernier mark with a stepper alignment sensor. Of the resist image is automatically measured (self-check). As a self-check method by a stepper,
For example, the measuring method of stepping accuracy disclosed in Japanese Patent Application Laid-Open No. 62-32614 can be used as it is. The measurement method is
After the mark formed on the test reticle is first exposed by the step-and-repeat method at a constant pitch in accordance with the design coordinate value, the wafer is left as it is, and overprinting is performed again by adding a fixed offset amount to the design coordinate value (double Exposure) and then development. Then, the relative positional deviation of the two mark resist images formed by a fixed amount within the area of each chip pattern is detected by the alignment sensor of the stepper, and the measured value is compared with the designed offset amount. Then, the stepping accuracy at the chip position is examined. This method is very convenient because stepping accuracy (stage positioning characteristics) is easily required, but requires high measurement reproducibility and high resolution of the alignment sensor. Therefore, diffraction grating marks for the x direction and the y direction measured by the interference alignment method are provided on the test reticle, and the marks are orthogonal to the grating pitch direction by a fixed amount within the chip pattern area on the wafer. The double exposure is performed in such a manner as to be offset in the direction more than the width of the grid mark and offset in the grid pitch direction by an integral multiple of the pitch.

When a single wafer is double-exposed and developed in a step-and-repeat manner in this manner, a group of lattice marks as shown in FIG. 11 is formed as a resist image in one chip pattern region. In FIG. 11, in the first exposure, a grid mark GRx measured in the x direction and a grid mark GRy measured in the y direction are formed. Before the second exposure, the wafer stage 3 is displaced by a predetermined amount in a diagonal direction of 45 °. Here, the intersection of each center line of the grid marks GRx and GRy is P
e, assuming that the grid pitch is Pg, the shift amount of the stage 3 is determined to be N · Pg (N is an integer) in each of the x direction and the y direction, and the intersection Pe moves to the intersection Pe ′. Then, the second exposure is performed, and the same grid mark on the reticle is marked GRx ′, GR
Formed on the wafer as y '. After the development is completed, the wafer is placed on the stage 3 of the stepper again, and global alignment is performed. Then, the relative position shift between the grid marks GRx and GRx ′ in the x direction by the interference type alignment sensor and the grid mark The relative displacement between GRy and GRy 'in the y direction is measured.

Generally, the stage used in this type of stepper has an extremely small stepping accuracy of 0.5 μm or less. Therefore, the lattice pitch Pg is set to 2 μm (1
(μm line and space), if the phase detection resolution is 1 °, a measurement resolution of about 2.8 nm can be obtained.

Incidentally, a method of measuring the misalignment of two grid marks arranged side by side on one wafer by a heterodyne method using interference fringes is, for example, a registration measurement disclosed in JP-A-62-56818. It can be implemented similarly.

By the above method, the alignment and stepper side
The sensor measures the misalignment of the lattice marks within ± 1/4 pitch of the lattice pitch Pg, stores it in the memory of the stepper, and uses the measured values at various positions on the wafer as a standard for random alignment errors. Deviation (σ _ux , σ _uy )
Should be obtained.

Further, the condition C is that the chip pattern on the wafer is a second or subsequent layer, and the layer is an ESA method (D / DA method or site-by-site alignment method or an alignment method using a position estimation filter). ). In this case, the reticle pattern to be exposed is
Exposure is performed by Method A. At this time, a special mark for registration measurement (for example, a grid mark in FIG. 11) is formed in advance in each chip pattern of the pilot wafer, and a reticle to be overlap-exposed is adjacent to the special mark. Then, a reticle pattern is formed so that the exclusive mark having the same shape is exposed.

Then, alignment marks (Mx, My) of several chips are measured by an alignment sensor of a stepper to be used, and exposure by the EGA method is performed. After that, the displacement of the pair of exclusive marks formed on the developed wafer is measured by another measuring device.
Alternatively, measure with an alignment sensor of a stepper.
This measured value is the total overlay error for each chip pattern, and the difference between the error amount and the positioning characteristic (stepping error) of the stage 3 is the array error of the chip pattern on the wafer. Therefore, similarly, the standard deviation of the random array error (σ _ux , σ _uy )
Can be calculated.

On the other hand, the standard deviation σ _w of the random measurement error can be obtained by the following two methods. In the first method, a reticle pattern is superposed and exposed on the pilot wafer by the ESA method, and registration of each chip pattern of the developed wafer is measured to obtain a superposition error. In this method, the measurement error of each chip pattern is obtained by subtracting the stage positioning characteristic obtained in advance from the overlay error. However, when the overlay exposure is performed by the site-by-site method among the ESA methods, random measurement errors can be found by the above method, but when the overlay exposure is performed by the D / DA method where the exposure position and the alignment position match. Is
The result of the registration measurement directly corresponds to a measurement error.

The second method can be performed when the standard deviation σ _u of the random arrangement error is known, and this method does not require test firing or use of a pilot wafer. First, several chips specified by the wafer EGA method to be overlaid are sample-aligned, and the measured coordinate values of the measured chips are measured. And the linear error parameter Is calculated and the predicted coordinate value of the measured chip is calculated. Is calculated. And the measured coordinate values And predicted coordinate values And the variance of the error And further dispersion And array error variance Is obtained, the variance of the random measurement error Is equivalent to

Therefore, if the deviation σ _{u of the} alignment error has been determined in advance, only some of the chip patterns on the wafer to be actually exposed are measured by the alignment sensor, and thereafter the deviation σ _w is determined only by calculation. be able to.

For example, when a manufacturing line is made up of a plurality of the same type of steppers, first, a unique positioning characteristic (stepping accuracy) of the stage of each stepper is obtained, and the standard deviation of the error is stored as σ _u . At this time, if there is a main computer that integrally controls a plurality of steppers, the deviation σ _u unique to each stepper is also stored therein. This is because exposure may be performed by changing the stepper for each layer on the wafer. For example, when the stepper A is overprinted on the wafer exposed by the stepper B,
The main computer sends the information of the deviation σ _u of the stepper B to the stepper A. In this way, for the first layer wafer and the wafer baked by the EGA method, in the actual wafer processing, all the steppers in the line perform sample alignment only, and random measurement errors The standard deviation σ _w can be determined. Also, for wafers baked using a position estimation filter, the variance of shot positions is become. This variance Is a sample if σ _u is previously determined as described above.
Calculation is possible only with alignment, and if the calculation result is sent as random array error data to a stepper that performs overlay exposure, the same effect can be obtained for a wafer burned through a position estimation filter. Overprinting with smoothing D / DA (or smoothing ESA) can be performed.

Here, the variance α ² is an estimated coordinate value when the wafer is burned through a position estimation filter. Are sequentially stored in memory, and their values are predicted coordinate values calculated by the EGA method. Can be obtained by simultaneously calculating how much variance (α ² ) has

〔The invention's effect〕

As described above, according to the present invention, a random position error component with respect to the design coordinates of the chip pattern and a random measurement error component included in the position measurement of the chip pattern are minimized, and high accuracy is achieved. Positioning becomes possible, and the productivity of semiconductor elements can be improved.

As a method of giving a deviation value (σ _ux , σ _uy ) of a random position error of a chip pattern or a deviation value (σ _wx , σ _wy ) of a random measurement error included in chip measurement,
It is possible to optimize the position estimation filter efficiently by measuring the superposition state of wafers processed by an exposure device such as a stepper with a dedicated measuring instrument and giving the statistically processed data to the stepper online. is there.

The present invention can be widely applied not only to a reduction projection type exposure apparatus but also to a 1: 1 projection stepper, a projection type stepper, a proximity type stepper, a photomask inspection apparatus, and the like.

Further, the present invention is also suitable for wafer alignment of a laser repair apparatus that does not use a reticle or a mask. The repair device blows a fuse having a width of about 1 to several μm formed in each chip on a wafer by irradiating it with a processing laser spot, and if a similar mark is left on the wafer. Global alignment,
The EGA method, the ESA method (in this case, only the site-by-site method) and the smoothing ESA method can be directly executed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of an alignment method according to an embodiment of the present invention, FIG. 2 is a perspective view showing a configuration of a stepper suitable for performing a method according to an embodiment of the present invention, and FIG. FIG. 4 is a view showing another configuration of the apparatus shown in FIG. 2, FIG. 4 is a plan view showing the arrangement of various alignment systems on the image plane of the projection lens, FIG. 5 is a plan view showing the state of global alignment of the wafer, FIG. FIG. 7 is a plan view showing a state of a random chip arrangement error, FIG. 7 is a view showing a state of mark detection in the apparatus of FIG. 2, and an example of a detected signal waveform, and FIG. Built into the device, the first
FIG. 9 is a block diagram showing the algorithm of the flowchart in hardware as hardware, and FIG. 9 is a graph comparing the positioning accuracy by the conventional method with the positioning accuracy by the method using the position estimation filter of the present embodiment. FIG. 10 is a plan view showing a chip arrangement for explaining another combination of the alignment chip selection and the exposure sequence, and FIG.
FIG. 12 is a plan view showing an arrangement of diffraction grating marks suitable for measuring stepping accuracy, overlay accuracy, and the like. FIG. 12 is a plan view of a chip arrangement showing a conventionally known alignment / exposure sequence. [Description of Signs of Main Parts] WA: Wafer, Mx, My: Mark, LB: Laser beam, LXS, LYS, YSP, θSP: Spot light, Cp: Chip pattern, R: Reticle, 1 …… Projection lens, 3 …… Wafer stage, 9,10 …… Laser interferometer, 20,21 …… Wafer global alignment system, 50 …… Main controller, 203
...... Error parameter determination unit, 204 EGA calculation unit, 206
… Stage controller, 207 …… Position estimation filter

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroshi Nozawa 2-8-4 Kitayuki, Nishi-ku, Yokohama-shi, Kanagawa Nikon System Corporation (56) References JP-A-1-243419 (JP, A) JP-A-Hei 1-135021 (JP, A) JP-A-63-310116 (JP, A) JP-A-63-232323 (JP, A) JP-A-62-137828 (JP, A) JP-A-61-44429 (JP, A) A) (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/027

Claims (7)

(57) [Claims] 1. A substrate on which a plurality of chip patterns arranged substantially regularly in accordance with an array coordinate on a design and alignment marks attached to each of the chip patterns are formed to be moved two-dimensionally. A method of sequentially aligning each of the plurality of chip patterns with respect to a predetermined reference position, comprising the steps of: (A) measuring coordinate positions of some of the chip patterns on the substrate; Creating an error parameter that the actual arrangement coordinate system of the chip patterns on the substrate has with respect to the design arrangement coordinate system based on the coordinates; and (B) the arrangement coordinates of the chip patterns on the substrate are A first statistic related to a random position error with respect to the array coordinates in the design, and a random number included in the measurement result when measuring the position of the mark of the chip pattern. Inputting a second statistic related to a measurement error; and (C) using the error parameter, the first statistic, and the second statistic to calculate an estimated coordinate value of the chip pattern. Creating a position estimation filter for output based on the law of least squares estimation; and (D) after the position estimation filter is determined, the measured coordinate values obtained by detecting the mark of the chip pattern are calculated. Positioning the substrate on the basis of the estimated coordinate value of the chip pattern input to the position estimation filter and output from the filter. 2. A two-dimensionally moving substrate on which a plurality of chip patterns arranged substantially regularly in accordance with design arrangement coordinates and alignment marks attached to each of the chip patterns is formed. In the method of sequentially aligning each of the chip patterns with respect to a predetermined reference position, (A) a first method relating to a random position error of actual array coordinates with respect to design array coordinates of the chip patterns on the substrate;
A step of previously obtaining and storing a statistic (σ _u ) and a second statistic (σ _w ) relating to a random measurement error included in the measurement result when the mark position of the chip pattern is measured by the position detecting means. (B) calculating the predicted coordinate value (Fn) of the n-th chip pattern on the substrate on the basis of the result of measuring the mark positions of at least three chip patterns on the substrate by the position detecting means; Determining parameters (R, O) for calculation from the value (Dn); and (C) the first statistic (σ _u ) is relatively large with respect to the second statistic (σ _w ). Determining a weighting factor (Q) that takes a large value when it becomes, and takes a small value when the first statistic (σ _u ) becomes relatively small with respect to the second statistic (σ _w ). And (D) the position detecting means. When there is a difference between the measured coordinate value (Gn) of the measured mark position and the predicted coordinate value (Fn), the weight between the measured coordinate value (Gn) and the predicted coordinate value (Fn) is obtained. The value corresponding to the coefficient (Q) is calculated as the estimated coordinate value (T
(E) calculating the mark position of the chip pattern on the substrate by the position detecting means, and then measuring the actual measured coordinate value (Gn), the predicted coordinate value (Fn), and the estimated coordinate. Positioning the substrate based on any one of the coordinate values of the value (Tn). 3. A two-dimensional substrate on which a plurality of chip patterns substantially aligned in accordance with a design array coordinate value (Dn) and alignment marks associated with each of the chip patterns are formed. A moving stage, coordinate measuring means for measuring the coordinate position of the stage, and detecting a mark on the substrate to detect a relative position of the chip pattern with respect to a predetermined reference point in cooperation with the coordinate measuring means An apparatus for sequentially aligning each of the chip patterns with respect to the reference point based on a detection result of the position detecting means, wherein a standard for random arrangement errors of the chip patterns on the substrate is provided. Q = σ _u ² / (σ _u ) based on the deviation (σ _u ) and the standard deviation (σ _w ) related to a random measurement error included in the measurement result by the position detection means. Storage means for storing a coefficient (Q) defined by the following relationship: ² + σ _w ² ); a linear error parameter (from a measured position of some chip patterns on the substrate detected by the position detection means) R, O) and the design coordinate value (Dn), and first calculation means for calculating respective predicted coordinate values (Fn) of the chip pattern defined by the relationship of Fn = R · Dn + O; On the basis of the actually measured coordinate value (Gn), the predicted coordinate value (Fn), and the coefficient (Q) of the chip pattern detected by the position detecting means, a relationship of Tn = Fn + Q · (Gn-Fn) is obtained. A second calculating means for calculating an estimated coordinate value (Tn) of each of the defined chip patterns; and so that the measured coordinates of the coordinate measuring means always have a unique relationship with the estimated coordinate value (Tn). Control means for controlling the positioning of the stage Aligning apparatus characterized by comprising and. 4. A method for aligning each of a plurality of chip patterns on a substrate in a predetermined coordinate system, comprising: selecting some of the plurality of chip patterns on the substrate; A first step of measuring a coordinate position of the chip pattern; and a second step of predicting a coordinate position of each of the plurality of chip patterns on the substrate based on the measured coordinate positions of the several chip patterns. And after the second step, a third step of actually measuring the coordinate position of the chip pattern to be aligned among the plurality of regions on the substrate; and, with respect to the chip pattern to be aligned, A fourth step of aligning the chip pattern to be aligned based on the coordinate positions predicted in the two steps and the coordinate positions actually measured in the third step. Alignment method according to claim. 5. A method of aligning each of a plurality of chip patterns on a substrate in a predetermined coordinate system, wherein the position of some of the plurality of alignment marks formed on the substrate is determined. A first step of detecting; a second step of predicting a coordinate position of each of a plurality of chip patterns on the substrate based on the detected positions of the several alignment marks; A third step of actually measuring the coordinate position of the chip pattern to be aligned among the plurality of chip patterns; information on a random measurement error when measuring the position of the mark on the substrate; and a chip on the substrate. The information on the chip pattern to be aligned is based on information on a random position error that the pattern arrangement has with respect to the design arrangement. A fourth step of determining weights for the coordinate position predicted in the second step and the coordinate position actually measured in the third step. 6. A method of aligning each of a plurality of chip patterns on a substrate in a predetermined coordinate system, wherein the position of some of the plurality of alignment marks formed on the substrate is determined. A first step of detecting; a second step of predicting a coordinate position of each of a plurality of chip patterns on the substrate based on the detected positions of the several alignment marks; The coordinates predicted in the second step when the random position error that the chip pattern arrangement has with respect to the design arrangement is larger than the random measurement error when measuring the position of the mark on the substrate. Determining a weight for a plurality of chip patterns on the substrate using the position. 7. A method for aligning each of a plurality of chip patterns on a substrate in a predetermined coordinate system, wherein the position of some of the plurality of alignment marks formed on the substrate is determined. Detecting; and estimating the coordinate position of each of the plurality of chip patterns on the substrate based on the detected positions of some of the alignment marks; and among the plurality of chip patterns on the substrate. Performing the alignment of the chip pattern to be aligned based on the predicted coordinate position and the actually measured coordinate position with respect to the chip pattern to be aligned. .