JPS6142987B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line scanning method in a communication control device, and more particularly to a method for automatically following a change in a connected line.

Conventionally, communication control devices have detected interrupts from connected lines by sequentially scanning boards assigned to each line.

However, in this method, even when a circuit is changed, that is, when a board corresponding to a certain circuit is removed because it is no longer needed, all circuits are always scanned, so time slots are wasted.

Therefore, the current method proposed is to selectively short-circuit between the scan counter output and the select decoder or between the ground and the select decoder using a short wire, as shown in FIG.

This method will be explained below with reference to FIGS. 2 and 3.

Here, to simplify the explanation, it is assumed that one line control board is equipped with control circuits for four lines, and in a device that can accommodate up to 32 lines (8 boards), An example in which 8 lines (2 boards) are connected will be explained.

In Fig. 1, 1 is a scanning counter that creates the time interval of time slots assigned to each board 0 to 7 (in this example, only mounted boards 0 and 1), and the clock shown in Fig. 3 A is input. By doing this, 1 is added corresponding to the line, and every 4 counts, the carry is increased and the count corresponding to the board is performed, and the number of pulses is 32, that is, when counting up to 7 with the count corresponding to the board, the value returns to 0. It is a nari counter.

2 is an output line of this scanning counter 1 having a weight of 4, 3 is an output line having a weight of 2, and 4 is an output line having a weight of 1. 5 and 6 are output lines for outputting 2-bit signals corresponding to the lines in each board.

7 is the output line 2, 3, 4 of the scanning counter 1.
A select decoder receives 3-bit signals from corresponding input lines 8, 9, 10 via short lines S ₁ , S ₂ , S ₃ , . . . and sends out time slots only to the selected board. In this example, the short line
Since S ₂ and S ₄ are shorted to ground, input line 8,
9 is always 0.

Reference numerals 11a to 11h are output lines from the select decoder 7, which are connected to corresponding boards.

12a and 12b are boards, and up to eight boards can be mounted. 13 is a line control circuit provided for each substrate 12a, 12b, . . . , 14 is an AND gate, and 15 is a common control circuit.

In this example, as mentioned above, the input lines 8 and 9 are always 0, so the signal input to the select decoder 7 only changes depending on whether the signal from the input line 10 is 1 or 0. As shown by the dotted lines in Figure 3, even though the time slots should originally be assigned to boards c to h, the short lines S ₂ and S ₄ are short-circuited to ground. ,
The signal is forcibly decoded to 0 or 1, and the time slots shown in FIG. 3 (b) and (c) are allocated only to the corresponding output lines 11a and 11b.

On the other hand, if an interrupt occurs in the line control circuit 13, the AND gate 14 opens, outputs, and sends a signal to the common control circuit 15.

The common control circuit 15 performs processing according to each line. In this way, in the current method, the short line
By selectively shorting S ₁ to _{S 6} to ground, the wasted time slots shown in FIGS.

Figure 2 is a diagram showing the combinations of open/close states of the short lines S ₁ to _{S 6} and the number of lines. The horizontal axis shows the number of lines, the vertical axis shows the short lines S ₁ to _{S 6} , and the 〇 mark at the intersection is When the number of lines is the same, the short line is closed and short-circuited, and when the number of lines is the same, the short line is opened.

With this configuration, unnecessary time slots are eliminated as described above.

However, in this method, when the number of connected lines increases to, for example, 12 lines (3 circuit boards), short lines S ₂ , S ₃ , and S ₅ are closed as shown in Figure 2, so the input line 8 will be short-circuited to ground, and a 2-bit signal (corresponding to 4 boards) will be input from input lines 9 and 10.

That is, 16 time slots were allocated, but lines 12, 13, 14, and 15 were not installed, and the corresponding four time slots were wasted. Similarly,
Even when the number of connected lines increased to 20, 24, and 28, there was a drawback that 12, 8, and 4 time slots were wasted, respectively.

Furthermore, each time the number of lines changes, the short lines S ₁ to S ₆ must be manually switched.

Therefore, the present invention provides a line scanning method that automatically allocates time slots only to installed lines.

FIG. 4 is a block diagram showing one embodiment of the present invention. In FIG. 4, 16 is a read-only memory (hereinafter referred to as ROM) that outputs input address information indicating whether or not a board is mounted and which board should be assigned a time slot, and 17 is a resistor.

In this example, a case will be explained in which a control circuit for four lines is mounted on one board, and in a device capable of controlling four boards, that is, 16 lines, the third board 12c is not mounted.

In this embodiment, the scan counter 1 counts from 1 to 16 and then returns to 0.

That is, a 2-bit signal is output from the output lines 3 and 2 every time four is counted, and signals 1 to 4 are sent to the lower two bits of the ROM 16. or
Resistors 17a, 17b, 17c, and 17d are connected to the upper input lines a, b, c, and d of the ROM 16, respectively, and when the corresponding board is inserted, they are connected to ground and input as a 0 signal, and the board When not inserted, +5V, for example, is input as one signal via a resistor.

That is, in this example, 0, 0, 1, 0, .

Now, to explain Fig. 5, Fig. 5 is
This shows the contents of the ROM 16, where the input addresses correspond to input terminals a to d in order from the top, and input addresses 00 to 03 indicate the case where all four boards are inserted. Therefore, the output is sequentially transmitted from substrate 0 (substrate 12a) to substrate 3 (substrate 1).
2d) to the select decoder 7 to allocate the time slot.

Next, input addresses 04 to 07 indicate the case where the board 12d is not mounted, and the outputs are 0, 1, 0, 2, indicating that time slots are assigned in the order of board 12a, board 12b, board 12a, and board 12c. It shows.

Next, input addresses 08 to 0B indicate the case where the board 12c is not mounted in this example.

That is, since the board 12c is not mounted, the input terminals of the ROM 16 have 0, 0, and
Enter 1, 0, X, X. X in the lower 2 bits,
For X, 2-bit signals 00, 01, 10, 11 are input sequentially from output terminals 2 and 3 of the scanning counter 1, so the above 2 bits together are 1000, 1001,
The input addresses are 1010 and 1011.

Therefore, the output of ROM16 is 0, 1, 0,
3, and the time slot that should originally be assigned to the board 12c is, as shown in FIG.
The substrate board 12b, the substrate 12a, and the substrate 12d are repeatedly allocated in this order.

As described above, according to the present invention, the output signal from the scanning counter that repeats counting within a predetermined range every time the clock is input and the signal generated depending on whether or not a board is mounted are used as input addresses of the ROM. , the output corresponding to the input address is assigned in advance as the output of this ROM, and the output of this ROM is
By decoding the output and assigning time slots to each line, time slots can be automatically assigned only to the installed lines, regardless of whether the board is mounted or not.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the conventional scanning method, Fig. 2 is a diagram showing the correspondence between short lines and the number of lines, Fig. 3 is a time chart showing the operation of Fig. 1, and Fig. 4 is a diagram showing the correspondence between short lines and the number of lines.
5 is a block diagram showing one embodiment of the present invention, FIG. 5 is a diagram showing an example of the contents of the ROM, and FIG. 6 is a time chart showing the operation of FIG. 4. 1... Scanning counter, 7... Select decoder, 12... Board, 15... Common circuit, 16...
ROM.

Claims (1)

[Claims] 1. An output signal from a scanning counter that repeats counting in a predetermined range every time a clock is input, and a signal generated depending on whether or not a board equipped with a line control circuit is mounted are used as input addresses of a read-only memory. The read-only memory is divided into multiple blocks according to the above-mentioned board mounting state, and information indicating only the mounted board is assigned as the contents of these blocks in the scanning order, and the output of this read-only memory is decoded to determine the mounted board. 1. A line scanning method in a communication control device, characterized in that time slots are assigned only to lines housed in a board.