CA1058764A - Serial data reception system - Google Patents
Serial data reception systemInfo
- Publication number
- CA1058764A CA1058764A CA259,503A CA259503A CA1058764A CA 1058764 A CA1058764 A CA 1058764A CA 259503 A CA259503 A CA 259503A CA 1058764 A CA1058764 A CA 1058764A
- Authority
- CA
- Canada
- Prior art keywords
- circuits
- serial data
- shift register
- bit positions
- reception system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/60—Semi-automatic systems, i.e. in which the numerical selection of the outgoing line is under the control of an operator
- H04M3/62—Keyboard equipment
Abstract
ABSTRACT OF THE DISCLOSURE
A serial data reception system comprises a multi-bit shift register for storing serial data while shifting them in response to clock pulses, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to the gate circuits, and a decoder connected to remaining bit positions of said shift register for enabling the gate circuits in a selected one of said plurality of reception circuits in accor-dance with the content of said remaining bit positions.
A serial data reception system comprises a multi-bit shift register for storing serial data while shifting them in response to clock pulses, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to the gate circuits, and a decoder connected to remaining bit positions of said shift register for enabling the gate circuits in a selected one of said plurality of reception circuits in accor-dance with the content of said remaining bit positions.
Description
)S87164 The present invention relates to a serial data reception system, and more particularly to a serial data recep-tion system adapted to be used in lamp indication of an atten-dant board connected to telephone exchange equipment.
An attendant board connected to telephone exchange equipment must exchange various data with the telephone ex-change equipment in order to carry out the telephonic exchange.
Heretofore, for sending such data from the telephone exchange equipment to the attendant board, one signal line has ~
..~ ... .:
been provided for each of the lamps or for each connection to numeric display elements, with the signal lines being con-trolled to a HIGH level or a LOW level for sending the data to the lamps or the numeric display elements of the attendant board. In this arrangement, however, when the number of the attendant boards increases or when various accessories are pro-vided on the attendant board, a large number of signal lines is required. As the number of signal lines increases, the control unit becomes complex. ~;
It is an~object of the present invention to eliminate the above drawback of the prior art arrangement and to provide an information reception system in which the number of signal lines between the telephone exchange equipment and attendant i;:
boards connected thereto does not depend on the number of ~ ;
attendant boards or the number of accessories mounted thereon. ;`
According to this invention there is provided a serial data reception system comprising; a shift register for storing serial data, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to said gate circuits, `~
a decoder connected to remaining bit positions of said shift register for enabling the gate circuits of a selected one of said reception d rcuits in accordance with the content of said ;~
~ \ ~ . .
remaining bit positions, and a control means for supplying timing pulses to said shift register and said decoder. ~
A feature of the present invention is that the lamps `
or the numeric display elements on the attendant board are c divided into groups, and serial data including data for the lamps or the numeric display elements as well as data for ;
specifying or addressing the groups is received by a shif-t register, from which the group specifying data is decoded to cause a memory circuit ~or the specified group to store the data for the lamps or th~ numeric display elements.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the accom-panying drawing, which shows a block diagram of an embodiment of the present invention used for lamp control of an attendant board. ;
Referring now to the drawing, a seria~1 data input ~--terminal 1 and a clock pulse input terminal 2 are connected to signal lines extending from telephone exchange equipment, not shown. The seriaI data input terminal 1 is coupled to a shift register 4 through a data receiver 3. The shift register 4 is of a 14-bit configuration, which shifts bit by bit in response to shift pulses fed from a clock pulse controller 5 through a wire 51. The clock pulse controller 5 is operated by an output `
of a clock pulse receiver 6 to which the clock pulse input terminal 2 is connected. 'h, :' .
160 lamps in an attendant board are divided into 15 `~
groups each comprising 10 lamps. Lamps LPO-LP9 of a No. 0~^;
circuit 100 are shown in the drawing. In the No. 0 circuit 100, A0-A9 designate 2-input AND gates the outputs of which are ;
respectively connected to set inputs S of flip-flops FFO-FF9 which form data memory circuits, respectively. Reset inputs R
':..`~
~1)S876~ ` `
of the flip-flops FFQ-FF9 are connected together and to a reset terminal RESET. Q outputs of the flip-flops FF0-FF9 are con- ;;
nected to lamp driver circuits LDO-LD9 the outputs of which are respectively connected to first terminals of the lamps LPO-LP9.
The second terminals of the lamps LPO-LP9 are connected together ' and to a battery B. While only the No. 0 circuit 100 is lllustrated in detail in the drawing, a No. 1 circuit 101 through a No. 15 circuit 115 are identically constructed.
The first 10 bit positions DO-D9 of the shift register 4 are connected in parallel to first inputs of the AND
gates A0-A9 of the No. 0 circuit 100 through the No. 15 cir-cuit 115. The remaining four bit positions Q0-Q3 of the shift ~ , register 4 are connected to a decoder 7, which upon reception of an instruction from the clock pulse controller 5 via a wire 52, produces a "1" output at one of its 16 outputs L0-L15 depending ;, on the content of the bits Q0-Q3 of the shift register 4. The 16 outputs of the decoder 7 are respectively connected to the second inputs of the AND gates A0-A9 of the No. O clrcuit 100 through the No. 15 circuit 115.
When fourteen bits of serial data comprising four bits ~, of address data follwed by ten bits of lamp on-off data are ?~ `' ' received at the data input terminal l from a central processing ~` `
unit of the telephone exchange equipment and clock pulses are received at the clock pulse input terminal 2, they are detected by the data receiver 3 and the clock pulse receiver 6, res-pectively. The serial data are shifted in the shift register 4 by shift pulses from the clock pulse controller 5 and stored therein. When the address data are stored in the bit positions 'h'.
~0-~3 of the shift register 4 and the lamp data are stored in ~
the lamp data bit positions D0-D9, the clock pulse controller 5 ` `
actuates the decoder 7 to cause it to decode the content of the !~
:
''" .
r~
11~5~376~
bit positions Q0-Q3 of the shift register 4. As a result, the decoder 7 produces a "1" output at one of the outputs L0-L15 !
Assuming now that the "1" output is produced at the output L01.
the AND gates A0-A9 of the No. 0 circuit 100 are enabled so that the contents of the lamp data bit positions D0-D9 of the shift register 4 are stored in the flip-flops FFO~FF9, which in turn actuate the lamp driver circuits LD0-LD9 to turn on or off the lamps LP0-LP9 depending on the contents of the lamp data bits.
The clock pulse controller 5 functions to deactuate the decoder 7 to cause the decoder 7 to be ready for the reception of the next incoming lamp data and the clock pulse. The flip- i^` ;
flops FF0-FF9 are reset at an appropriate time.
As seen from the illustrated embodiment, the present invention can control any number of lamps, and/or numeric display elements which can be employed instead of the lamps L20-LP9, with two signal lines, one for the clock pulses -:
and the other for the data. Consequently, the transmission of information between the exchange equipment and the attendant board can be carried out with a smaller number of signal lines than that required in the prior art arrangement, and the number of signal lines required in the present invention is not affected by the number of the attendant boards and the number of the accessories. ;
Furthermore, because the data are first stored in the buffer or shift register and thence transferred to the flip-flops of the corresponding group, flickering of the lamps or numeric ~`
display element, which otherside occurs due to the transfer~
is eliminated and the control unit can be simplified. When a ,.,;
higher processing rate is desired, the transfer clock frequency ~`
may be raised or an additional buffer may be provided between the ~;
:;, ... .
exchange equipment and the attendant board to share the groups.
_ 4 ~
... .. .
An attendant board connected to telephone exchange equipment must exchange various data with the telephone ex-change equipment in order to carry out the telephonic exchange.
Heretofore, for sending such data from the telephone exchange equipment to the attendant board, one signal line has ~
..~ ... .:
been provided for each of the lamps or for each connection to numeric display elements, with the signal lines being con-trolled to a HIGH level or a LOW level for sending the data to the lamps or the numeric display elements of the attendant board. In this arrangement, however, when the number of the attendant boards increases or when various accessories are pro-vided on the attendant board, a large number of signal lines is required. As the number of signal lines increases, the control unit becomes complex. ~;
It is an~object of the present invention to eliminate the above drawback of the prior art arrangement and to provide an information reception system in which the number of signal lines between the telephone exchange equipment and attendant i;:
boards connected thereto does not depend on the number of ~ ;
attendant boards or the number of accessories mounted thereon. ;`
According to this invention there is provided a serial data reception system comprising; a shift register for storing serial data, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to said gate circuits, `~
a decoder connected to remaining bit positions of said shift register for enabling the gate circuits of a selected one of said reception d rcuits in accordance with the content of said ;~
~ \ ~ . .
remaining bit positions, and a control means for supplying timing pulses to said shift register and said decoder. ~
A feature of the present invention is that the lamps `
or the numeric display elements on the attendant board are c divided into groups, and serial data including data for the lamps or the numeric display elements as well as data for ;
specifying or addressing the groups is received by a shif-t register, from which the group specifying data is decoded to cause a memory circuit ~or the specified group to store the data for the lamps or th~ numeric display elements.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description with reference to the accom-panying drawing, which shows a block diagram of an embodiment of the present invention used for lamp control of an attendant board. ;
Referring now to the drawing, a seria~1 data input ~--terminal 1 and a clock pulse input terminal 2 are connected to signal lines extending from telephone exchange equipment, not shown. The seriaI data input terminal 1 is coupled to a shift register 4 through a data receiver 3. The shift register 4 is of a 14-bit configuration, which shifts bit by bit in response to shift pulses fed from a clock pulse controller 5 through a wire 51. The clock pulse controller 5 is operated by an output `
of a clock pulse receiver 6 to which the clock pulse input terminal 2 is connected. 'h, :' .
160 lamps in an attendant board are divided into 15 `~
groups each comprising 10 lamps. Lamps LPO-LP9 of a No. 0~^;
circuit 100 are shown in the drawing. In the No. 0 circuit 100, A0-A9 designate 2-input AND gates the outputs of which are ;
respectively connected to set inputs S of flip-flops FFO-FF9 which form data memory circuits, respectively. Reset inputs R
':..`~
~1)S876~ ` `
of the flip-flops FFQ-FF9 are connected together and to a reset terminal RESET. Q outputs of the flip-flops FF0-FF9 are con- ;;
nected to lamp driver circuits LDO-LD9 the outputs of which are respectively connected to first terminals of the lamps LPO-LP9.
The second terminals of the lamps LPO-LP9 are connected together ' and to a battery B. While only the No. 0 circuit 100 is lllustrated in detail in the drawing, a No. 1 circuit 101 through a No. 15 circuit 115 are identically constructed.
The first 10 bit positions DO-D9 of the shift register 4 are connected in parallel to first inputs of the AND
gates A0-A9 of the No. 0 circuit 100 through the No. 15 cir-cuit 115. The remaining four bit positions Q0-Q3 of the shift ~ , register 4 are connected to a decoder 7, which upon reception of an instruction from the clock pulse controller 5 via a wire 52, produces a "1" output at one of its 16 outputs L0-L15 depending ;, on the content of the bits Q0-Q3 of the shift register 4. The 16 outputs of the decoder 7 are respectively connected to the second inputs of the AND gates A0-A9 of the No. O clrcuit 100 through the No. 15 circuit 115.
When fourteen bits of serial data comprising four bits ~, of address data follwed by ten bits of lamp on-off data are ?~ `' ' received at the data input terminal l from a central processing ~` `
unit of the telephone exchange equipment and clock pulses are received at the clock pulse input terminal 2, they are detected by the data receiver 3 and the clock pulse receiver 6, res-pectively. The serial data are shifted in the shift register 4 by shift pulses from the clock pulse controller 5 and stored therein. When the address data are stored in the bit positions 'h'.
~0-~3 of the shift register 4 and the lamp data are stored in ~
the lamp data bit positions D0-D9, the clock pulse controller 5 ` `
actuates the decoder 7 to cause it to decode the content of the !~
:
''" .
r~
11~5~376~
bit positions Q0-Q3 of the shift register 4. As a result, the decoder 7 produces a "1" output at one of the outputs L0-L15 !
Assuming now that the "1" output is produced at the output L01.
the AND gates A0-A9 of the No. 0 circuit 100 are enabled so that the contents of the lamp data bit positions D0-D9 of the shift register 4 are stored in the flip-flops FFO~FF9, which in turn actuate the lamp driver circuits LD0-LD9 to turn on or off the lamps LP0-LP9 depending on the contents of the lamp data bits.
The clock pulse controller 5 functions to deactuate the decoder 7 to cause the decoder 7 to be ready for the reception of the next incoming lamp data and the clock pulse. The flip- i^` ;
flops FF0-FF9 are reset at an appropriate time.
As seen from the illustrated embodiment, the present invention can control any number of lamps, and/or numeric display elements which can be employed instead of the lamps L20-LP9, with two signal lines, one for the clock pulses -:
and the other for the data. Consequently, the transmission of information between the exchange equipment and the attendant board can be carried out with a smaller number of signal lines than that required in the prior art arrangement, and the number of signal lines required in the present invention is not affected by the number of the attendant boards and the number of the accessories. ;
Furthermore, because the data are first stored in the buffer or shift register and thence transferred to the flip-flops of the corresponding group, flickering of the lamps or numeric ~`
display element, which otherside occurs due to the transfer~
is eliminated and the control unit can be simplified. When a ,.,;
higher processing rate is desired, the transfer clock frequency ~`
may be raised or an additional buffer may be provided between the ~;
:;, ... .
exchange equipment and the attendant board to share the groups.
_ 4 ~
... .. .
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A serial data reception system comprising:
a shift register for storing serial data, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to said gate circuits, a decoder connected to remaining bit positions of said shift register for enabling the gate circuits of a selected one of said reception circuits in accordance with the content of said remaining bit positions, and a control means for supplying timing pulses to said shift register and said decoder.
a shift register for storing serial data, a plurality of reception circuits each including gate circuits connected to certain bit positions of said shift register and memory circuits connected to said gate circuits, a decoder connected to remaining bit positions of said shift register for enabling the gate circuits of a selected one of said reception circuits in accordance with the content of said remaining bit positions, and a control means for supplying timing pulses to said shift register and said decoder.
2. A serial data reception system according to claim 1 wherein at least one of the reception circuits includes a lamp coupled to each of said memory circuits.
3. A serial data reception system according to claim 1 wherein at least one of the reception circuits includes a numeric display element coupled to said memory circuits.
4. A serial data reception system according to claim 1, 2, or 3 wherein each of said memory circuits comprises a flip-flop.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122575A JPS5225507A (en) | 1975-08-22 | 1975-08-22 | Data transfer expansion system to transit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1058764A true CA1058764A (en) | 1979-07-17 |
Family
ID=14294943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,503A Expired CA1058764A (en) | 1975-08-22 | 1976-08-20 | Serial data reception system |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5225507A (en) |
| AU (1) | AU497491B2 (en) |
| CA (1) | CA1058764A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120206A (en) * | 1977-03-29 | 1978-10-20 | Nec Corp | Attendant board control system for electronic switchboard |
| JPS53129908A (en) * | 1977-04-19 | 1978-11-13 | Fujitsu Ltd | Terminal control system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS512706Y2 (en) * | 1971-05-22 | 1976-01-26 | ||
| JPS492778A (en) * | 1972-03-13 | 1974-01-11 |
-
1975
- 1975-08-22 JP JP10122575A patent/JPS5225507A/en active Pending
-
1976
- 1976-08-20 CA CA259,503A patent/CA1058764A/en not_active Expired
- 1976-08-20 AU AU17008/76A patent/AU497491B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| AU497491B2 (en) | 1978-12-14 |
| JPS5225507A (en) | 1977-02-25 |
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