JPS6142927A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6142927A
JPS6142927A JP59165309A JP16530984A JPS6142927A JP S6142927 A JPS6142927 A JP S6142927A JP 59165309 A JP59165309 A JP 59165309A JP 16530984 A JP16530984 A JP 16530984A JP S6142927 A JPS6142927 A JP S6142927A
Authority
JP
Japan
Prior art keywords
bonding
partition plate
fine
bonding pad
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59165309A
Other languages
Japanese (ja)
Inventor
Tetsuo Hoshino
星野　哲雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP59165309A priority Critical patent/JPS6142927A/en
Publication of JPS6142927A publication Critical patent/JPS6142927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To allow connection of a plurality of fine bonding wires easily and securely by dividing a plurality of fine bonding wires connecting electrodes of a semiconductor element and tip members of lead wires into a group of a lower layer and a group of an upper layer and providing an insulating partition plate between these groups. CONSTITUTION:After lines of bonding pads 6 and 6' in a semiconductorelement and lines of tip members of stichlands 3 are selected not less than two, and the bonding pad 6 of the first line near the periphery and the tip member of the stichland in the inside thereof are connected with each other by a fine bonding wire 5, a partition plate 9 is made to adhere with an insulating adhesive 10 so as to cover the bonding wire 5 with the insulating partition plate 9. After this, a bonding pad 6' of the second line and a tip member of a stichland are connected by a fine bonding wire 11. This causes the fine bonding wire to be double layer, which allows multi-connection without narrowing the dimension or the interval of the bonding pad.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置のボンディング部の構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a bonding portion of a semiconductor device.

、　（従来の技術） 従来、Ｃ０Ｂ（チップ・オン・ボード）と呼ばれている
半導体装置は、第２図に示す様に絶縁性基板１の上にメ
ッキ、エツチング等や技術でＣｕ。(Prior Art) Conventionally, a semiconductor device called C0B (chip on board) is made by depositing Cu on an insulating substrate 1 by plating, etching, etc., as shown in FIG.

Ｎｉ、Ａｕ等の積層構造の導電パターン２を形成しこの
導電パターン２の一部のステッチ２ンド部３と絶縁性基
板１上に搭載した半導体素子４とを複数のボンディング
用細線５で結線している。さらに１図示はしていないが
、この半導体素子４と導電パターン２の一部とボンディ
ング用細ａＳとを樹脂で封止している。A conductive pattern 2 having a laminated structure of Ni, Au, etc. is formed, and a part of the stitch 2 bond part 3 of this conductive pattern 2 is connected to a semiconductor element 4 mounted on an insulating substrate 1 using a plurality of thin bonding wires 5. ing. Furthermore, although not shown, the semiconductor element 4, a part of the conductive pattern 2, and the bonding thin aS are sealed with resin.

ここで従来用いられて来たボンディング部の構造は半導
体素子部のポンディングパッド６の位置が外周に一列に
並んでいる。In the structure of the bonding portion conventionally used here, the positions of the bonding pads 6 of the semiconductor element portion are aligned in a line on the outer periphery.

（発明が解決しようとする問題点） この構造の欠陥はボンディング細線５の数が増えるに従
い、ポンディングパッドの寸法７６るいは間隔８を狭め
なければならない事である。即ちポンディングパッドの
寸法７あるいは間隔８０寸法が小さくなると、ワイヤー
ボンディング装置のボンディング位置精度あるいはボン
ディング強度上の問題から半導体素子４上にボンディン
グできないという事態が生じる。(Problems to be Solved by the Invention) A drawback of this structure is that as the number of bonding thin wires 5 increases, the dimension 76 of the bonding pads or the spacing 8 must be reduced. That is, if the dimension 7 of the bonding pad or the dimension 80 of the spacing becomes small, a situation arises in which bonding cannot be performed on the semiconductor element 4 due to problems with the bonding position accuracy or bonding strength of the wire bonding device.

本発明の目的はよシ多くのボンディング細線で半導体素
子と外部リード先端部とが容易かつ確実に結線可能な半
導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a semiconductor element and an external lead tip can be connected easily and reliably with a large number of bonding wires.

（問題点を解決するための手段） 本発明は半導体素子のポンディングパッド列とステッチ
ランドの列とをそれぞれ２Ｍにし、外側のポンディング
パッドと内側のステッチランドとを結ぶポンディング細
線の上に絶縁仕切板を介して内側のポンディングパッド
と外側のステッチランドとを結ぶボンディング細線を多
層に配置する事に！！Ｄ、ポンディングパッド寸法ある
いハピッチを狭める事なくして多数のボンディング細線
の結線を可能くしたものである。(Means for Solving the Problems) The present invention has a bonding pad row of a semiconductor device and a stitch land row of 2M each, and a bonding pad line connecting an outer bonding pad and an inner stitch land. We decided to arrange multiple layers of thin bonding wires that connect the inner bonding pad and the outer stitch land via an insulating partition plate! ! D. It is possible to connect a large number of thin bonding wires without narrowing the bonding pad size or the pitch.

（実施例） 次Ｋ、図面を参照して本発明をよシ詳細に説明する。第
１図に本発明の一実施例を示す。半導体素子内のポンデ
ィングパッド６．６１の列およびステッチ２ンド３の先
端部の列をそれぞれ２列以上とし、外周部−列のポンデ
ィングパッド６と内側のステッチランド３先端部とをボ
ンディング細線５で接続した後ポンディング細線５を絶
縁仕切板９でおおうように仕切板９を絶縁性接着材工０
で接着する。この後２列目のポンディングパッド６′と
ステッチランド先端部とをボンディング細線１１で結線
する。(Example) Next, the present invention will be explained in more detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The number of rows of bonding pads 6 and 61 in the semiconductor element and the rows of the tips of the stitch lands 3 are two or more, respectively, and the bonding pads 6 in the outer periphery row and the tips of the stitch lands 3 on the inside are bonded with thin wires. After connecting the bonding thin wires 5 with the insulating partition plate 9, attach the partition plate 9 with an insulating adhesive material 0.
Glue with. Thereafter, the bonding pad 6' of the second row and the tip of the stitch land are connected with the bonding thin wire 11.

（発明の効果） このようにボンディング細線を２層にすることによって
ポンディングパッドの寸法あるいは間隔を狭める事なし
に多結線化が可能となる。また、絶縁仕切板９によって
ポンディング細線同志が短絡することもない。(Effects of the Invention) By forming the bonding thin wires into two layers in this manner, it is possible to increase the number of wire connections without narrowing the dimensions or spacing of the bonding pads. Further, the insulating partition plate 9 prevents the bonding thin wires from being short-circuited.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図に＋　、　ＣＢ＋　、　（Ｃ）は本発明の一実施
例を示す図で、同図１４１は最初のワイヤーボンディン
グ終了後の素子近傍の平面図、同図の）は２回目のワイ
ヤーポンディング終了後の素子近傍の一部平面図、同図
（Ｃ）は同図の）のＡ−Ａ’断面の構造を示す断面図で
ある。 第２図（Ａ）　、　（Ｂｌは従来の半導体装置の素子近
傍の平面図およびＡ−Ａ’断面での断面図である。 １・・・絶縁性基板、２・・・導電パターン、３・・・
導電パターンステッチランド部、４・・・半導体素子、
５・・・ボンディング細線、６・・・ポンディングパッ
ド、７・・・ポンディングパッド寸法、８・・・ポンデ
ィングパッド間隔、９・・・絶縁仕切板、１０・・・絶
縁性接着材、１１・・・ボンディング細線。In FIG. 1, +, CB+, and (C) are diagrams showing one embodiment of the present invention. Figure 141 is a plan view of the vicinity of the element after the first wire bonding is completed, and ) in the same figure is a diagram showing the second wire bonding. FIG. 2 is a partial plan view of the vicinity of the element after completion of the process, and FIG. FIG. 2(A), (Bl is a plan view of the vicinity of an element of a conventional semiconductor device and a cross-sectional view taken along the AA' cross section. 1. Insulating substrate, 2. Conductive pattern, 3.・・・
Conductive pattern stitch land portion, 4... semiconductor element,
5... Bonding thin wire, 6... Bonding pad, 7... Bonding pad dimensions, 8... Bonding pad spacing, 9... Insulating partition plate, 10... Insulating adhesive material, 11... Bonding thin wire.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の電極とリード線先端部とを結線する複数の
ボンディング細線を下層の群と上層の群とに分け、これ
らの群の間に絶縁仕切板を設けた事を特徴とする半導体
装置。A semiconductor device characterized in that a plurality of thin bonding wires connecting electrodes of a semiconductor element and lead wire tips are divided into a lower layer group and an upper layer group, and an insulating partition plate is provided between these groups.
JP59165309A 1984-08-07 1984-08-07 Semiconductor device Pending JPS6142927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59165309A JPS6142927A (en) 1984-08-07 1984-08-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59165309A JPS6142927A (en) 1984-08-07 1984-08-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6142927A true JPS6142927A (en) 1986-03-01

Family

ID=15809882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59165309A Pending JPS6142927A (en) 1984-08-07 1984-08-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6142927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05321286A (en) * 1991-07-31 1993-12-07 Kobe Steel Ltd Ultra-low speed control device of excavating machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05321286A (en) * 1991-07-31 1993-12-07 Kobe Steel Ltd Ultra-low speed control device of excavating machine

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