JPS6142648U

JPS6142648U - channel device

Info

Publication number: JPS6142648U
Application number: JP11866985U
Authority: JP
Inventors: 辰夫岡田; 正仁日原
Original assignee: 富士通株式会社
Priority date: 1985-08-01
Filing date: 1985-08-01
Publication date: 1986-03-19

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本箸案の一実施例の構成を示す図、第２図は第
１図の動作ブローチャートを示す，１・・・中央処理装
置、２・・・チャネル装置、３・・・専用領域、４・・
・サブチャネルワード、５・・・先頭アドレスレジスタ
、６・・・最ｉアドレスレジスタ、７・・・入出力装置
機番レジスタ、２１・・・送受信制御部、２２・・・割
込み制御部。FIG. 1 is a diagram showing the configuration of an embodiment of the proposed chopsticks, and FIG. 2 is a flowchart of the operation of FIG. 1. 1...Central processing unit, 2...Channel device, 3... Dedicated area, 4...
- Subchannel word, 5... Starting address register, 6... Most i address register, 7... Input/output device machine number register, 21... Transmission/reception control section, 22... Interrupt control section.

Claims

[Claims for Utility Model Registration] Connecting input/output devices corresponding to subchannels, controlling the interrupt queue for the central processing unit, and in the subchannel world assigned to each input/output device number,
In a channel device having an interrupt instruction bit and a program interrupt instruction bit, a dedicated area is provided for storing interrupt input/output device machine numbers in the order of interrupt occurrence, and regarding storage in the dedicated area, input/output at the head of the interrupt queue is provided. an address register that specifies the storage area for the device number;
An address register is provided that indicates a storage area for the last input/output device number, and when an interrupt to the central processing unit occurs, the interrupt instruction bit or the program interrupt instruction bit corresponding to the generated input/output device number is set. and means for storing the interrupt input/output device number in the dedicated area based on the last input/output device number in the interrupt queue and an address register indicating a storage area, and increments the address register. When interrupt permission is granted from the central processing unit, the number of the first input/output device in the interrupt queue is stored using the address register that specifies the storage area for the first input/output device number. A channel device characterized in that it performs interrupt processing by comprising means for determining the address register and incrementing the address register according to the interrupt instruction bit or the program interrupt instruction bit.