JPS54116856A - Byte multiplexer channel unit - Google Patents
Byte multiplexer channel unitInfo
- Publication number
- JPS54116856A JPS54116856A JP2348878A JP2348878A JPS54116856A JP S54116856 A JPS54116856 A JP S54116856A JP 2348878 A JP2348878 A JP 2348878A JP 2348878 A JP2348878 A JP 2348878A JP S54116856 A JPS54116856 A JP S54116856A
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- queue
- address
- register
- sbcm3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
Abstract
PURPOSE: To secure an interrupt process in terms of time by generating a queue for a program control interrupt and by attaining the program control interrupt according to this queue.
CONSTITUTION: To an ordinary multiplexer channel unit, register FIQR6 stored with the head IO address of an interrupt queue and register LIQR7 stored with the tail IO address of the interrept queue are both attached. Sub-channel register SBCR of subchannel memory SBCM3 is provided with an area in which interrupt-pending information, registration information and the address of an IO causing the next interrupt are stored. If an interrupt is caused with reference to one IO, interrupt- pending information and registration information as to SBCR equivalent to the IO are read out to work register WR4 and then set to SBCM3. When the interrupt request is the 1st one, the address of the IO is set to FIOR6 and when the queue is generated, the address of the IO is set to LIOR7 and SBCM3. Then, the interrupt process is performed.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53023488A JPS5845731B2 (en) | 1978-03-03 | 1978-03-03 | Byte multiplexer channel device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53023488A JPS5845731B2 (en) | 1978-03-03 | 1978-03-03 | Byte multiplexer channel device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54116856A true JPS54116856A (en) | 1979-09-11 |
JPS5845731B2 JPS5845731B2 (en) | 1983-10-12 |
Family
ID=12111891
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53023488A Expired JPS5845731B2 (en) | 1978-03-03 | 1978-03-03 | Byte multiplexer channel device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5845731B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6142648U (en) * | 1985-08-01 | 1986-03-19 | 富士通株式会社 | channel device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50111948A (en) * | 1974-02-12 | 1975-09-03 |
-
1978
- 1978-03-03 JP JP53023488A patent/JPS5845731B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50111948A (en) * | 1974-02-12 | 1975-09-03 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6142648U (en) * | 1985-08-01 | 1986-03-19 | 富士通株式会社 | channel device |
Also Published As
Publication number | Publication date |
---|---|
JPS5845731B2 (en) | 1983-10-12 |
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