JPS6142346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and particularly to a static type semiconductor memory device.

There are two types of semiconductor memory devices depending on their mode of operation: static type and dynamic type. In dynamic semiconductor memory,
Information is stored in a MOS capacitor or a PN junction capacitor, and it is easy to obtain a memory device with a high degree of integration, large capacity, and low power consumption, but the charge accumulated in the capacitor becomes the center of recombination in the semiconductor. It is captured and gradually decreases with a certain time constant. Therefore, it is necessary to perform a so-called refresh operation periodically within the time determined by the time constant, which has the disadvantage that control of memory peripheral circuits and operation timing is complicated.

On the other hand, static semiconductor memory requires a constant current to flow through each memory cell to retain stored information, so it consumes a lot of current and has a large number of elements in each cell, making it unsuitable for large-capacity memories. However, since the above-mentioned refresh operation is not necessary, a memory device with a small capacity such as 4K bits is used.

It is an object of the present invention to provide a static type semiconductor memory device which can reduce power consumption, which is a problem peculiar to static type memories, and which can be highly integrated.

A PN junction formed between a low concentration semiconductor substrate and a high concentration impurity region of opposite conductivity type formed in the substrate is
When the PN junction is in a no-voltage state, a so-called barrier voltage unique to the PN junction exists between its ends, and the barrier voltage V _B is significantly smaller than that of the impurity region N _B when the substrate concentration N _A is In this case, it is shown by the following formula.

V _B ≒q・_NA・W _P ² /2ε (1) q is the electronic charge, W _P is the width of the depletion layer, and ε is the dielectric constant of the semiconductor.

Therefore, in the present invention, the barrier voltage V _B is set higher than the threshold voltage V _T of a semiconductor switching element such as an insulated gate field effect transistor (IGFET), and the threshold voltage V is externally applied to the PN junction as necessary. The configuration is such that a reverse voltage lower _{than T} is applied, and the IGFET is
This was based on the knowledge that it is possible to control on/off.

The present invention will be explained below with reference to the accompanying drawings.

FIG. 1 is a diagram explaining the principle of the present invention,
An N-channel MOS type transistor representing an IGFET is used as a switch element, and FIG. 2 is a schematic cross-sectional view of the circuit shown in FIG. 1. Gate electrode A of transistor Q ₄ is P-type silicon substrate 1
It is connected to N type impurity region 5b inside. Transistors Q ₁ and Q ₂ of the same conductivity type with this impurity region 5b as a common electrode region are provided in series between the current source I ₀ and the ground as shown in the figure, and their gate electrodes G are commonly connected to each other and the switch _SW A control voltage V _G is applied via. Note that the element isolation region 2 shown at 3 in FIG. 2 is a field insulating film.

In such a configuration, when switch _SW is open, transistors Q ₁ and Q ₂ are both off, and there is no voltage between the PN junction between substrate 1 and impurity region 5b. Therefore, the transistor
The barrier voltage V _B of the PN junction is applied to the gate A of Q ₄ , and this voltage V _B is applied to the gate A of the transistor Q ₄ .
This transistor Q ₄ can be turned on by setting the threshold value V _T to be larger than the threshold value V T . Here,
Substrate concentration N _A ≒5×10 ¹⁴ /cm ³ and N _A ≪N _B
(N-type impurity concentration), V _B can be approximately 1.54 ^V from equation (1). Furthermore, the width of the depletion layer W _P
≒2μm.

Also, if the concentration of only the channel region of the transistor is 10 ¹⁵ /cm ³ , then the fermi potential φ
If _F is 0.273V and the gate film thickness is 600A, the threshold voltage V _T can be approximately 0.84V. Therefore, V _T <V _B and transistor Q ₄ can be turned on.

On the other hand, the switch _SW is closed and the transistor
If Q ₁ and Q ₂ are turned on, transistors Q ₁ and
Current flows through Q ₂ from current source I ₀ . At this time, the drain current _ID of transistors Q ₁ and Q ₂ is expressed by the following equation.

_ID = εox/tox・μW/L・[(V _G −V _T )・V _D− 〓V _D ² ] ………(2) Here, εox is the dielectric constant of the gate film, tox is its thickness, μ is the mobility (=1000 cm ³ /Vsec), W/L is the ratio of channel width to length (≈2), and V _D is the drain voltage. If I _D =0.4 μA (=I ₀ ), then V _D =5.74 mV from equation (2). Since this voltage V _D is clearly significantly smaller than the threshold value V _T of transistor Q ₄ , transistor Q ₄ can be turned off.

The third device constructed a static type semiconductor memory cell using the devices shown in FIGS. 1 and 2.
This is the circuit shown in the figure. In this figure, all N
It is constructed using channel MOS type transistors, and a first current path is formed by transistors Q ₁ and Q ₂ connected in series, and a second current path is similarly formed by transistors Q ₃ and Q ₄ . Both current paths are provided in parallel between the current source I ₀ and ground, and the gate electrodes of transistors Q ₁ and Q ₂ are connected to _the series connection point of transistors Q ₃ and Q ₄ . The gate electrode of _Q4 is connected to the series connection point A of transistors _Q1 and _Q2 .

The series connection point A is connected to one B of a pair of column lines, that is, input/output information lines B, through a bidirectional switch transistor _Q5 , and the series connection point is connected to the other information line through a switching transistor _Q6 . connected to. and both transistors
The gate electrodes of Q ₅ and Q ₆ are connected to the row selection line W. At this point, transistors Q ₁ and Q ₂ become conductive and the first
The case where the current flows in the second current path is set as "0", and the case where the transistors Q ₃ and Q ₄ are conductive and the current flows in the second current path is set as "1".

During the write operation, the row line W becomes "1",
If the write information is “1”, bit line B is “1”,
is “0”, so the potential at point A is “1”,
The potential of becomes "0". Therefore the transistor
Since Q ₃ and Q ₄ are turned on, a predetermined current flows in the second current path. In this state, when the row line W returns to "0", the transistors Q ₅ and Q ₆ are turned off, so the point becomes "0". Considering the other point A, since transistor Q ₅ is off and transistors Q ₁ and Q ₂ are also off,
Point A is completely unaffected by external potential.
Therefore, the barrier voltage of the PN junction mentioned earlier V _B = 1.54V
is applied to the gates of transistors Q ₃ and Q ₄ ,
While both transistors remain on, the second
Current will flow in the current path.

At this time, the voltage drop due to transistor Q ₄ , that is, the drain voltage V _D is 5.74 mV, as mentioned above.
Therefore, no current flows through the first current path where both transistors Q ₁ and Q ₂ are turned off. Therefore, "1" is written into the memory cell.

At the time of reading, the row line W becomes "1", and the column lines B,
1.54V (“1”) and 5.74mV (“0”) are read out respectively.

FIG. 4 shows a memory circuit using the memory cells shown in FIG. Rows and columns (m x n bits)
It is obvious that the present invention applies to memory devices such as the above. The first and second current paths of the memory cell _M1 in the first row in the figure are connected to the current source _I0 and the next memory cell as shown in the figure.
It is connected in parallel with _M2 . Therefore, the parallel connection circuits of the first and second current paths of each of the memory cells M ₁ to _{M 4} belonging to the same column are connected in series between the current source and a predetermined reference voltage line, such as the ground line. ing.

FIG. 5 shows a transistor Q ₁ constituting a first current path in a memory cell M ₁ of a semiconductor memory device.
and _Q2 , for example, high concentration N-type regions 5a, 5b, selectively provided on a P-type silicon substrate 1 with an impurity concentration of 5×10 ¹⁴ /cm ³ .
5c, gate insulating film 4, and further gate electrode 8
(), both transistors
Q ₁ and Q ₂ are commonly connected by sharing the impurity region 5b.

In the figure, 3 is a high-concentration P-type region for isolation between elements, 2 is a field insulating film, and 7 is a single-layer wiring and 2
This is an insulating film between layer wiring.

If 128 unit cells are connected in series, the total voltage drop will be 128 x 5.74 mV = 735 mV, which is smaller than the threshold voltage V _T = 0.84 _V. 0.735V is applied to the memory cell _M1 , and the cell _M1 can maintain the "1" state without turning on the transistors _Q1 and _Q2 .

In reality, considering that the threshold voltage V _T varies due to manufacturing reasons, etc., I _D = 0.2 by removing Yosuke.
If it is μA, then V _D =2.86 mV, and the overall voltage drop is 0.366 V. There is a margin between V _T =0.84 V and reliable operation can be expected. Therefore, the current is 0.2 μA per column, and for example, in the case of 128 columns, it is sufficient to use a constant current source I ₀ of 128×0.2 μA=25.6 μA.

At the time of reading, the row line _W1 becomes "1", transistors _Q5 and _Q6 are turned on, and the column line B is turned on.
1.54V (“1”) is read out, while 0.366V (“0”) is read out. Therefore, it is possible to discriminate between "1" and "0" by using a sense amplifier that performs a comparison with, for example, 1V.

FIG. 6 is a cross-sectional view showing the manufacturing process of the device shown in FIGS. 4 and 5. First, P with a concentration of 5×10 ¹⁴ /cm ³
Prepare a mold silicon substrate 1, and cover the entire surface with a thick oxide film 2.
form a. Thereafter, the oxide film corresponding to the isolation region is selectively etched to introduce P-type impurities to form a highly concentrated P-type isolation region 3 (a).

After forming an oxide film over the entire surface, the oxide film in the portion where the gate insulating film is to be formed is removed. At this time, in order to obtain an appropriate threshold voltage, for example, boron is introduced so that the concentration of the channel part is 10 ¹⁵ /cm ³ .
Thereafter, an oxide film 4a of 400 Å is deposited.
A silicon nitride film 2b with a thickness of 200 Å is formed on top of it, but since the gate insulating film is made as thin as possible in order to increase the conversion conductance of the gate, impurities in the polycrystalline silicon that will be formed later will penetrate into the oxide film. This is to prevent deterioration of the properties as an insulating film, and to use it as a stopper when plasma etching polycrystalline silicon (b).

Then, the insulating film in the portions that should become the source and drain regions is removed, and the source and drain regions 5a to 5a are removed.
5c, and a polycrystalline silicon layer 6 to become a first layer wiring is formed on the entire surface (c). The polycrystalline silicon layer 6 is selectively etched into a predetermined wiring shape to form a first layer wiring (d).

Then, an oxide film 7a and a silicon nitride film 7b are formed on the entire surface (e), and then contact holes for the first and second layer wiring are formed, and a polycrystalline silicon layer that will become the second layer wiring is covered on the entire surface. After depositing, the desired wiring shape is etched (f) to obtain the device shown in FIG.

Note that this manufacturing method is merely an example, and various well-known techniques can be used.

With this configuration, the isolation width can be reduced to 2
If μ, the cell size for 1 bit is 30μ×45
A 128 x 128 bit (16K) unit cell can be housed in a 4 mm x 6 mm chip. This is because although the degree of integration is significantly improved compared to the conventional six-element static memory, there is no need for a power supply line for each cell.

Furthermore, current consumption can be significantly reduced to 0.2 μA×128 = 25.6 μA, making it possible to reduce power consumption.

In the above example, an N-channel type semiconductor element is used, but it is clear that a P-channel type element is also applicable.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram explaining the principle of the present invention, Figure 2 is a circuit diagram explaining the principle of the present invention.
3 is a memory cell circuit diagram showing an embodiment of the present invention, FIG. 4 is a memory circuit diagram using the memory cell of FIG. 3, and FIG. 5 is a sectional view of the circuit device shown in FIG. Fig. 4 is a partial sectional view of the circuit device, and Fig. 6 is a partial cross-sectional view of the circuit device.
FIG. 3 is a cross-sectional view of each part of the device shown in the figure in the order of manufacturing steps. Explanation of symbols of main parts, _Q1 to _Q6 ...transistor, _I0 ...current source, W...row line, B,...column line.

Claims (1)

[Scope of Claims] 1. A switch element, a PN junction formed in a semiconductor substrate and having a barrier voltage sufficient to make the switch element conductive when no voltage is applied, and a PN junction that makes the switch element conductive when no voltage is applied. 2. A semiconductor memory device comprising means for applying a predetermined voltage sufficient to cause the switch element to change, the barrier voltage being one of the binary information of the circuit, and the predetermined voltage being a control voltage of the switch element. 2 including first and second transistors connected in series to form a first current path, and third and fourth transistors connected to each other in series to form a second current path; A series connection point of the two transistors is connected to gate electrodes of the third and fourth transistors, a series connection point of the third and fourth transistors is connected to gate electrodes of the first and second transistors, and a series connection point of the third and fourth transistors is connected to the gate electrodes of the first and second transistors. and a second current path is connected between the current source and a predetermined reference potential point, the first to fourth transistors are insulated gate field effect transistors of the same conductivity type formed on the same semiconductor substrate, and the Each of the series connection points is connected to the semiconductor substrate in the semiconductor substrate.
A semiconductor memory device characterized in that the impurity region forms a PN junction, and a barrier voltage of the PN junction is used as one of binary information of a circuit. 3. memory cells arranged in a matrix of m rows and n columns, each having a pair of switching elements for reading and writing, and a pair of information lines belonging to each of the columns and respectively connected to the pair of switching elements; The static memory device includes m control lines that selectively make the switching elements conductive, wherein each of the memory cells has first and second control lines connected in series to form a first current path. a transistor, and third and fourth transistors connected in series to each other forming a second current path, the series connection point of the first and second transistors being connected to the gate electrodes of the third and fourth transistors. and connected to one of the switching elements, and a series connection point of the third and fourth transistors is connected to the first and second transistors.
connected to the gate electrode of the transistor and to the other of the switching elements;
and a second current path are connected in parallel to each other, and furthermore, a parallel connection circuit of the first and second current paths of each memory cell belonging to the Nth column (N is an integer from 1 to n) is connected to a predetermined current. the first to third electrodes of each memory cell are connected in series between a source and a predetermined reference potential point;
The fourth transistor is an insulated gate field effect transistor of the same conductivity type formed on the same semiconductor substrate, and each of the series connection points is an impurity region forming a PN junction with the semiconductor substrate in the semiconductor substrate, A semiconductor memory device characterized in that the barrier voltage of the PN junction is one of the binary information of the circuit.