Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co LtdfiledCriticalFuji Electric Co Ltd
Priority to JP8152085UpriorityCriticalpatent/JPS614202U/ja
Publication of JPS614202UpublicationCriticalpatent/JPS614202U/ja
Application grantedgrantedCritical
Publication of JPS6343526Y2publicationCriticalpatent/JPS6343526Y2/ja
Synchronising circuit for timing signal using cascaded flip=flops - uses one flip=flop as polarity detector of signal and connects to second via delay by logic