JPS6141296A - Exchange switch system - Google Patents

Abstract

PURPOSE:To set easily the timing for decision of the time distribution which is needed to fix a writing address, by providing a function to shift and write data in the order of input when the data are written on an exchange switch memory. CONSTITUTION:The write data of the 1st channel emerges at WD1-8 when data are written on a memory. Thus all memory elements M1.1-Mn.8 are set under a writing-enable state by the input of a clock WCP synchronized with said write data. Then the data of the 1st channel are written on those memory elements. Then the write data of the 2nd channel emerge at WD1-8 and the clock WCP is supplied. Thus the elements M1.1-Mn.8 are set again under a writing enable state, and the data of the 1st channel written previously on those memory elements are shifted to adjacent memories Mn-1.1-Mn-1.8. Thus the data of the 2nd channel are written newly on the elements Mn.1-Mn.8. Hereafter, the same procedure is repeated until the write data of the n-th channel emerges. Finally the data of the n-th, (n-1)-th and 1st channels are written on memory elements Mn.1-Mn.8, Mn-1.1-Mn-1.8 and M1.1-M1.8 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a circuit system for a switching switch in a time division switching device.

(2) Prior Art Conventionally, the exchange switch part of a time-sharing exchange device has generally been configured mainly around memory, but in this case, # reading of the data to be exchanged is synchronized with the synchronization clock of the write data. Write addresses are sequentially generated starting from address 1 using a counter circuit that operates as a counter circuit, and the write data is written into the memory in accordance with the designation of the write address. On the other hand, for reading the data, a circuit system is adopted in which the read data is taken out in accordance with the designation of read addresses that occur in a prespecified order.

Therefore, in order to operate the exchangeable switch memory, it is necessary to consider the time margin required for determining the address both at the time of writing and at the time of reading, and the timing of the exchangeable switch peripheral circuit that requires high-speed operation is necessary. This makes management extremely difficult. Further, the circuit configuration is complicated, such as requiring a write address generation circuit. - (3) Purpose of the Invention The present invention, in a time division exchange switch system, makes it unnecessary to specify an address when writing data to a memory circuit, thereby making the timing control of the memory and memory control circuit, etc. The purpose is to simplify the circuit configuration.

(4) Structure of the Invention The above object is to write data to the exchange switch memory by sequentially shifting the write data word by word in the order of input in the address direction to address 1, address 2, address 3, etc. Data reading is achieved by using a circuit system that outputs read data based on address designation, similar to a normal memory.

(5) Embodiment of the present invention Next, an embodiment of the present invention will be described with reference to the drawings. Figure 1 is a circuit diagram showing an embodiment of a memory section used as an exchange switch, taking as an example the case where one channel exchanges digital signals of 8 bits. The exchange capacitor is an n-channel.

In Figure 1, WD 1 and WD B are write data, WCP is a synchronization clock for write data, and RD1 to R
Dg is read data, RA1 to RAMm are address data at the time of reading, DEC is a binary code decoder, A
1 to An represent read data designation signals, Ml- to Nagi, 8 each represent a 1-pit storage element, G1, 1 to Gn, and 8 represent an AND gate.

In FIG. 1, when inputting exchange data, that is, when writing data into memory, WD 1 , WD
When the write data of the first channel appears in B, all the memory elements Ml,t~Nagi,8 become ready for writing by the input of the clock WCP synchronized with it, Mn,l.
The data of the first channel is written to zhln,8. Next, the write data of the second channel is WD1~
When it appears in WD8 and WCP is input, Ml, 1-
M5, s is in the storage ready state, and the previous K Mn,
l-Mn, s, IIC The data of the first channel written is the adjacent Mn-1, 1 to Mn-5, s
The data of the second channel is newly written to Mn- to Mn,a. After that, the same operation is repeated until the n-th channel's gluteal data appears, and finally, the n-th channel Mn-t
, s to Mn-t, s are written for the n-1st channel..., Mt, lNMl, and s are each data of the first channel.

Next, a detailed description will be given of the time of outputting exchange data, that is, the time of reading data from the memory. When read addresses are input to RA'l~RAm in the order corresponding to the channel to be replaced, one of A1~An of the decoder DEC
A read data designation signal is output from one. For example, when a designated signal appears on An-1, Gn-x, x ~ Gn
Only the 8 AND gates -s, s open. Therefore, the stored data of Mn-1,t to Mn-1,11 is RDI
-Output to RD8. Similarly, one of A1 to An is specified one by one according to the addresses that appear one after another in RAI to RAm, and the corresponding storage data is stored in RD1.
~RD8 are sequentially output.

As a result of the above, this implementation array can arrange and output digital signals of n-channel 8-bit configuration in an arbitrary order channel by channel, which is similar to the case of using a conventional random access memory with n-word 8-bit groove configuration. Can work as a replacement switch.

In this way, according to the present invention, when data is written to one memory, the shift register is operated by the synchronized clock of the written data, and when data is read, it is formed as a shift register that operates according to the synchronized clock of the written data.
By using a circuit system that extracts data tg in response to address designation, similar to the 7 dumb access memory, it has a complete function as an exchange switch, and moreover, address designation is not required when writing data. Therefore, it is possible to solve the difficulty in allocating address confirmation time during a short cycle time. At the same time, there is an advantage that the circuit configuration can be simplified, such as eliminating the need for an address control circuit.

(7) Effects of the Invention The present invention facilitates timing design for determining the time allocation required to determine the write address by providing a function to shift the data to the memory for the exchange switch in the order in which the data is input. This has the effect of omitting the write address control circuit.

[Brief explanation of the drawing]

Figure 1 shows an n-channel 8-bit digital configuration. 1 is a block diagram of an embodiment of the present invention for a data exchange switch; FIG. WDI to WD8...Write data, WCP.
...Write data synchronization clock, RD1~R
D8...Read data, RA1~RAm...
...Address data when reading, f) EC...
...Binary code decoder, A1-An... Read data designation signal, Ml--Mn, s...
1-bit storage elements each, G1. s~Gn, 8
...and gate. $1 1!21

Claims (1)

[Claims] When writing data to a memory circuit for a time division exchange switch, the storage element in the memory operates as a shift register in the address direction and sends the data into the memory in the order of input, and when reading data, the data corresponds to the specified address. An exchange switch method characterized by outputting.