JPS6141130B2 - - Google Patents
Info
- Publication number
- JPS6141130B2 JPS6141130B2 JP14674079A JP14674079A JPS6141130B2 JP S6141130 B2 JPS6141130 B2 JP S6141130B2 JP 14674079 A JP14674079 A JP 14674079A JP 14674079 A JP14674079 A JP 14674079A JP S6141130 B2 JPS6141130 B2 JP S6141130B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- substrate
- point metal
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
本発明は、高融点金属を材料とした電極を有す
る半導体装置を製造するのに好適な方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method suitable for manufacturing a semiconductor device having an electrode made of a refractory metal.
近年、ゲート電極、その他配線にモリブデン
（Mo），タングステン（Ｗ）などの高融点金属が
用いられている。その理由は、それ等金属材料が
低抵抗であること、精密なパターニングが可能で
あるなど加工性に優れていること、電極・配線形
成後の熱処理温度に充分耐え得ることなどが主な
ものである。 In recent years, high melting point metals such as molybdenum (Mo) and tungsten (W) have been used for gate electrodes and other wiring. The main reasons for this are that these metal materials have low resistance, have excellent workability such as being able to be precisely patterned, and can sufficiently withstand heat treatment temperatures after forming electrodes and wiring. be.
ところが、例えばMoをMIS電界効果トランジ
スタのゲート電極として用いた場合、シリコン
（Si）・二酸化シリコン（SiO2）界面の準位を増し
たり、可動イオンの影響で閾値電圧（Vth）が印
加電圧に依つて動くなど、安定性が低下する問題
を生じる。その原因は、装置の製造工程、特にフ
オト・レジストを用いたパターニングの工程に於
いて、そのフオト・レジストに含まれるナトリウ
ム・イオン（Na+）や重金属が依り汚染されるこ
とが主たるものである。尚、Mo，Ｗは所謂柱状
結晶をなし、ポーラスであるから、汚染物質はそ
の皮膜を貫通して容易にSiO2膜に到達すること
ができる。 However, for example, when Mo is used as the gate electrode of a MIS field effect transistor, the level at the silicon (Si)/silicon dioxide (SiO 2 ) interface increases, and the threshold voltage (Vth) changes due to the influence of mobile ions. This causes problems such as a decrease in stability, such as movement. The main reason for this is that sodium ions (Na + ) and heavy metals contained in the photoresist become contaminated during the device manufacturing process, especially the patterning process using photoresist. . Incidentally, since Mo and W form so-called columnar crystals and are porous, contaminants can easily penetrate the film and reach the SiO 2 film.
本発明は、高融点金属を材料とする電極・配線
を有し、しかも、Na+などの汚染がない半導体装
置を容易に製造する方法を提供するものであり、
以下これを詳細に説明する。 The present invention provides a method for easily manufacturing a semiconductor device that has electrodes and wiring made of a high-melting point metal and is free from contamination such as Na + .
This will be explained in detail below.
本発明では、Moなど高融点金属の電極・配線
を有する半導体装置を製造する際、高融点金属の
蒸着を水素を含む雰囲気中で行なうことに依り高
融点金属を変質させ、、絶縁膜中の可動イオンの
もととなる汚染物質を取込み難いようにすること
が基本になつている。水素を含む雰囲気中で高融
点金属の蒸着膜を形成すると何故前記のような性
質が現われるのか明確な理由は未だ不明であるが
実験的に確認することは容易である。 In the present invention, when manufacturing a semiconductor device having electrodes and wiring made of a high-melting point metal such as Mo, the high-melting point metal is evaporated in an atmosphere containing hydrogen to change the quality of the high-melting point metal, and The basic idea is to make it difficult for pollutants, which are the source of mobile ions, to be taken in. Although the exact reason why the above-mentioned properties appear when a vapor-deposited film of a high melting point metal is formed in an atmosphere containing hydrogen is still unclear, it is easy to confirm experimentally.
本発明一実施例を第１図乃至第８図を参照しつ
つ説明する。 An embodiment of the present invention will be described with reference to FIGS. 1 to 8.
第１図参照
(1) 比抵抗例えば７〜10〔Ω―cm〕であるｐ型シ
リコン半導体基板１上に例えば熱酸化法を適用
して厚さ例えば500〔Å〕の二酸化シリコン膜
２を形成する。Refer to Figure 1 (1) A silicon dioxide film 2 having a thickness of, for example, 500 [Å] is formed by applying, for example, a thermal oxidation method on a p-type silicon semiconductor substrate 1 having a specific resistance of, for example, 7 to 10 [Ω-cm]. do.
(2) 例えば化学気相成長法を適用して厚さ例えば
1000〔Å〕の窒化シリコン膜３を形成する。(2) For example, by applying chemical vapor deposition
A silicon nitride film 3 with a thickness of 1000 [Å] is formed.
(3) 通常のフオト・リソグラフイ技術にて二酸化
シリコン膜２及び窒化シリコン膜３のパターニ
ングを行ない、能動領域上に在るもののみを残
し他を除去する。(3) The silicon dioxide film 2 and the silicon nitride film 3 are patterned using ordinary photolithography technology, leaving only those on the active region and removing the others.
第２図参照
(4) 例えば温度1100〔℃〕、湿性酸化雰囲気、時
間２〔時間〕の熱処理を行ない、所謂選択酸化
に依り厚さ例えば8000〔Å〕のフイールド用絶
縁膜４を形成する。Refer to FIG. 2 (4) A heat treatment is performed at a temperature of, for example, 1,100 [° C.] in a humid oxidizing atmosphere for a time of 2 [hours] to form a field insulating film 4 having a thickness of, for example, 8,000 [Å] by so-called selective oxidation.
第３図参照
(5) 浸漬法に依り、二酸化シリコン膜２及び窒化
シリコン膜３を除去して基板１の能動領域表面
を露出させる。Refer to FIG. 3 (5) The silicon dioxide film 2 and the silicon nitride film 3 are removed by a dipping method to expose the surface of the active region of the substrate 1.
第４図参照
(6) 例えば温度1000〔℃〕、乾燥酸化雰囲気、時
間45〔分〕の熱処理を行なつて厚さ例えば400
〔Å〕のゲート絶縁膜４Ｇを形成する。Refer to Figure 4 (6) For example, heat treatment is performed at a temperature of 1000 [℃], in a dry oxidizing atmosphere, for a time of 45 [minutes], and the thickness is 400 [℃].
A gate insulating film 4G having a thickness of [Å] is formed.
第５図参照
(7) 電子ビーム蒸着法を適用し、厚さ例えば3000
〔Å〕のMo膜５を形成する。この際、蒸着室内
にはMoソース及び基板１を配設し、真空度を
１〜５×10-7〔Torr〕以下とし、そこに水素
（H2）を導入することに依り内圧を１〜50×
10-6〔Torr〕とした状態でMoソースを電子ビ
ームで加熱し基板１上にMo膜５を形成する。
尚、前記蒸着室内の内圧は電子ビーム蒸着を行
なつている間はそれを同程度に維持することが
望ましい。See Figure 5 (7) Apply electron beam evaporation to a thickness of, for example, 3000 mm.
A Mo film 5 of [Å] is formed. At this time, a Mo source and a substrate 1 are placed in the deposition chamber, the degree of vacuum is set to 1 to 5 × 10 -7 [Torr] or less, and hydrogen (H 2 ) is introduced thereto to reduce the internal pressure to 1 to 5 × 10 -7 [Torr]. 50×
10 -6 [Torr], a Mo source is heated with an electron beam to form a Mo film 5 on the substrate 1.
Incidentally, it is desirable that the internal pressure in the vapor deposition chamber be maintained at the same level while electron beam vapor deposition is being performed.
第６図参照
(9) 通常のフオト・リソグラフイ技術を適用して
フオト・レジスト・マスク６を形成し、Mo膜
５のパターニングを行ない、Moゲート電極５
Ｇを形成する。このパターンニングでは高融点
金属特有の精密性はそのまま維持されている。Refer to FIG. 6 (9) A photoresist mask 6 is formed by applying ordinary photolithography technology, the Mo film 5 is patterned, and the Mo gate electrode 5 is formed.
form G. This patterning maintains the precision characteristic of high melting point metals.
第７図参照
(10) イオン注入法を適用し、n+型ソース領域７
Ｓ、n+型ドレイン領域７Ｄを形成する。この
時の注入イオンは砒素イオン（A8 +）、注入エ
ネルギ150〔KeV〕、ドーズ量４×1015〔cm-2〕
であつた。See Figure 7 (10) Applying ion implantation method, n + type source region 7
An S, n + type drain region 7D is formed. The ions implanted at this time were arsenic ions (A 8 + ), implantation energy 150 [KeV], and dose 4×10 15 [cm -2 ].
It was hot.
第８図参照
(11) 化学気相成長法を適用し、例えば二酸化シリ
コン絶縁膜８を形成する。Refer to FIG. 8 (11) For example, a silicon dioxide insulating film 8 is formed by applying chemical vapor deposition.
(12) 通常の蒸着法、フオト・リソグラフイ技術を
適用し、例えばアルミニウム（Al）のソース
電極９Ｓ及びドレイン電極Ｄの形成する。(12) A source electrode 9S and a drain electrode D made of, for example, aluminum (Al) are formed by applying a normal vapor deposition method or photolithography technique.
このようにして作製した装置及び従来装置に於
ける二酸化シリコン・ゲート絶縁膜中の可動イオ
ン量を測定すると本発明方法に依る場合、１×
1011〔cm-2〕以上であつた。可動イオン量の測定
は、基板を温度240〔℃〕に保ち、Moゲート電極
に正、基板に負の電圧を印加し、ゲート絶縁膜中
を流れるイオン電流を測定することに依り行なつ
た。前記本発明実施例に依る装置ではゲート電極
に印加する電圧に依つてVthが変動することはな
かつた。 When measuring the amount of mobile ions in the silicon dioxide gate insulating film in the device manufactured in this way and the conventional device, when using the method of the present invention, 1×
It was over 10 11 [cm -2 ]. The amount of mobile ions was measured by keeping the substrate at a temperature of 240 [°C], applying a positive voltage to the Mo gate electrode and a negative voltage to the substrate, and measuring the ion current flowing through the gate insulating film. In the device according to the embodiment of the present invention, Vth did not vary depending on the voltage applied to the gate electrode.
第９図は蒸着中のH2分圧と可動イオン（×1011
〔em-2〕）の関係を表わす線図である。 Figure 9 shows the H2 partial pressure during vapor deposition and mobile ions (×10 11
[em -2 ]) is a diagram showing the relationship between
この図からすると、蒸着中に加えるH2は多い
程良いように考えられるが余り多くなると電子ビ
ームの走行が妨げられ、蒸着効率が低下すること
になる。 From this figure, it seems that the more H 2 added during vapor deposition, the better; however, if too much H 2 is added, the electron beam will be hindered, and the vapor deposition efficiency will decrease.
以上の説明で判るように、本発明に依れば、高
融点金属の電極・配線を有する半導体装置を製造
する際、半導体基板への高融点金属膜の被着を水
素を含む雰囲気中で行うことにより高融点金属を
変質させ、絶縁膜中の可動インのもととなる汚染
物質を取込み難くすることにより、絶縁膜中の可
動イオン量は大幅に減少し、Si・SiO2界面の準位
が増したり、Vthが変動するなどの不安定性を解
消した半導体装置を得ることができる。 As can be seen from the above description, according to the present invention, when manufacturing a semiconductor device having electrodes and wiring made of a high melting point metal, a high melting point metal film is deposited on a semiconductor substrate in an atmosphere containing hydrogen. This alters the quality of the high-melting point metal and makes it difficult for contaminants, which are the source of mobile ions in the insulating film, to be taken in. As a result, the amount of mobile ions in the insulating film decreases significantly, and the level at the Si/SiO 2 interface decreases. It is possible to obtain a semiconductor device in which instability such as an increase in Vth or a fluctuation in Vth is eliminated.
第１図乃至第８図は本発明一実施例を説明する
為の工程要所に於ける半導体装置の要部側断面
図、第９図は可動イオンと水素の関係を表わす線
図である。
図に於いて、１は基板、４は絶縁膜、４Ｇはゲ
ート絶縁膜、５Ｇはモリブデン・ゲート電極、６
はゲート電極形成の為のフオト・レジスト・マス
ク、７Ｓはソース領域、７Ｄはドレイン領域、８
は絶縁膜、９Ｓはソース電極、９Ｄはドレイン電
極である。
1 to 8 are side cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 9 is a diagram showing the relationship between mobile ions and hydrogen. In the figure, 1 is a substrate, 4 is an insulating film, 4G is a gate insulating film, 5G is a molybdenum gate electrode, 6
is a photoresist mask for forming a gate electrode, 7S is a source region, 7D is a drain region, 8
9 is an insulating film, 9S is a source electrode, and 9D is a drain electrode.
Claims (1)
を製造する方法に於いて、前記高融点金属の皮膜
を水素雰囲気中で基板上に該金属を蒸着して形成
する工程が含まれることを特徴とする半導体装置
の製造方法。1. A method for manufacturing a semiconductor device having electrodes and wiring made of a high melting point metal, characterized by including a step of forming a film of the high melting point metal on a substrate by vapor depositing the metal on a substrate in a hydrogen atmosphere. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14674079A JPS5670646A (en) | 1979-11-13 | 1979-11-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14674079A JPS5670646A (en) | 1979-11-13 | 1979-11-13 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5670646A JPS5670646A (en) | 1981-06-12 |
| JPS6141130B2 true JPS6141130B2 (en) | 1986-09-12 |
Family
ID=15414515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14674079A Granted JPS5670646A (en) | 1979-11-13 | 1979-11-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5670646A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272232U (en) * | 1988-11-18 | 1990-06-01 | ||
| DE102022118209A1 (en) | 2021-07-27 | 2023-02-02 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device and semiconductor manufacturing equipment |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931065A (en) * | 1982-08-16 | 1984-02-18 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS6083373A (en) * | 1983-10-14 | 1985-05-11 | Nec Corp | Thin film transistor array and manufacture thereof |
-
1979
- 1979-11-13 JP JP14674079A patent/JPS5670646A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272232U (en) * | 1988-11-18 | 1990-06-01 | ||
| DE102022118209A1 (en) | 2021-07-27 | 2023-02-02 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device and semiconductor manufacturing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5670646A (en) | 1981-06-12 |
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