JPS6139979A - Control device of magnetic disk - Google Patents

Abstract

PURPOSE:To shorten processing time of a magnetic disk by being equipped with a means containing write-in information into initialized data forming a data format, initializing the magnetic disk and simultaneously writing in write-in information. CONSTITUTION:When a magnetic disk FD8 is set to a magnetic disk drive device (FDD) 7 and initialization and a write-in command of information are executed by an order from a keyboard. CPU3, first, sends a restoring command to a magnetic disk controller (FDC) 6 based upon a control program. FDC6 sends a control signal to FDD7, a head of FDD7 is shifted to a position of an outermost side of FD8 and a detecting circuit is sent to FDC6. Next, CPU3 sends a write track command to FDC6 and further, initialized data and write-in information are sent to FDC6. FDC6 converts to a serial signal, transfers to FDD7, initializes a data format to FD8 and simultaneously, writes in an the processing time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The fifth aspect of the present invention is to control the reading and writing of a magnetic disk (hereinafter referred to as FD) such as a flexible day support cartridge to a magnetic disk control device.

(Prior Art) Conventionally, in order to write information such as data and programs to an FD, two processing steps were required: first, initializing the FD to form a data format, and then writing information in accordance with the data format. Ta. Therefore, when writing information to an FD for the first time, or when writing information after forming a data format again, several minutes of processing time is required.

(Object of the Invention) The present invention was invented to eliminate the above-mentioned drawbacks, and its purpose is to simultaneously write information when forming an FDI data format.
An object of the present invention is to provide a control device for some disks that can significantly shorten FD processing time.

(Configuration and Embodiments of the Invention) FIG. 1 is a block diagram showing the basic electrical configuration of a magnetic disk control device 1 according to the present invention, and FIG. 2 is a partial block diagram showing information transmission relationships. Magnetic disk control device 1
The operation of the CP is performed by commands from the keyboard 2.
A control program stored in the ROM 4 is called by U3, and based on this control program, a 7-lexiple disk controller (hereinafter referred to as F'l) C or magnetic disk controller is executed via the CPU interface 5. ) 6, and a flexible disk drive device (hereinafter referred to as FDD or magnetic disk drive device) controlled by this FDC 6.
7, information is written to F'D8 and FD
Eight pieces of information are read out. The information written to FD8 is transferred from FDC6 to FDD7 as a serial signal.
is transmitted by a write information signal line (WD) 10 to
Information read from FD8 is sent to FD as a serial signal.
A read information signal line (RAWREA) is connected from D7 to FDC6.
D) transmitted by 11.

The information read and written to the FD8 is transferred to the CPU interface 5 and the FDC as parallel data via an 8-bit bidirectional data access line (D, -D, >12).
Transmission is performed between the two.

The transmission relationship of these pieces of information is shown in the block diagram of FIG.

FIG. 3 is a block diagram showing the configuration of the FDC 6.

The data output rose 7713 is a buffer 7 that connects information read from the FDD 7 to the bidirectional data access line 12. The data shift register (DSR) 14 is an 8-bit serial shift register, and temporarily stores read information from the FDD 7 and write information from the CPU interface 5 as serial data.

The data register (DR) 15 is parallel data from 8 bits that can be written and read, and when the FDC 6 is in read operation, 1 from the data shift register 14
When a byte of parallel data is loaded into the data register 15 and the FDC 6 is in a write operation, the contents of the data register 15 are loaded in parallel into the data shift register 14.
loaded into.

The command register (CR) 1G is a write-only 8-bit register, and a command is written into the command register 16 from the CPU 3 side according to the operation desired to be executed by the FDC 6.

The main commands and an overview of their operations are shown below.

(Command) (Overview of command operations) Restore... Move the head to track "00" on the disk Seek... Move the head to the specified track Step... Move the head one track inside or outside the disk Read data...Write data to read data from the disk...Read address to write data to the disk...Read track to read the ID field of the disk ...Write track that reads all data for one track on the disk...The track register (TR) 17 that writes data for one track on the disk is an 8-bit shift register that can be written and read, and is normally , is used so that the track number of the head position of the FD8 is held.

The sector register (SCR) 18 is a writable and readable 8-bit shift register.
In a write data command, a target sector number is written prior to instruction execution.

CR' C (C' yclic Redundancy)
y Cfleck) circuit 19 checks whether there is any erroneous writing or erroneous 6 selling in the serial pit cell (16 bit data) transferred between the FD 8 and the FD 8. When writing to FD8, CR from write data
Automatically generate C data and externally write CRC data to FD8. Furthermore, when reading from FI) 8, C and RC data are reproduced from the serial pit cells and errors are checked. In the illustrated example of the data format shown in FIG. 4, which will be described later, when writing, the AM
(1) Consider the bit string from the first bit of (ID ADDRESS MARK) 31 to the last bit of data of ID 32 as a binary polynomial, divide this polynomial by a specific binary polynomial, and calculate the remainder as CRC (1 )33 as I
Continuously write data after D32. Similarly DA
The bit string from the first bit of AM(2) 36 of the TA field 41 to the last bit of DATA 37 is
Divide by the hex polynomial and write the remainder continuously after DATA 37 as CRC(2) 38.

Symbols (a) and (b) shown in FIG. 4 indicate CRC, and (c) indicates ID data, that is, address and sector capacity.

The arithmetic unit (ALU) 20 has the functions of serial data comparison, increment (+1), decrement (-1), and through (+0), and performs operations such as updating the contents of each register, checking with the register, and comparing the magnitude. Do the following.

The status register (STR) 42 is a read-only 8
It is a bit register, and its contents change depending on the type of command that has already been written to the command register 16 and is being executed. Therefore, by reading the status register 42 from the CPU side, the internal state of the FDC 6,
In other words, the state of the FDD 7 can be known.

The address mark detection (A\detection) circuit 21 is a circuit that detects data having a specific bit pattern from among the serial bit cells transferred from the FD8, and the detected data is an index mark I DM28.
, ID32 address mark, etc.

FIG. 4 shows an example of a data format in the case of single density (FM) applied to the embodiment of the present invention, in which the track 22 consists of a preamble section 23, 26 sectors 24, and a post-preamble section 25. be done. Preamble part 23 is GAP(0)26.5YNC(1)2
7, I DM (INDEX MARK) 28, GA
They are arranged in the order of P(1)29, and the number of bytes and data contents of each area are as shown in the figure. Note that the data contents are attenuated by hexadecimal numbers, and the symbol * indicates that there is a missing clock.

The sector part 24 is 5YNC (2) 30, AM (1) (ID
ADDRESS'MARK>31, ID32, C
ID field 40 consisting of RC(1) 33 and GAP
(2) 34, 5YNC (3) 35, AM (2) (DA
TA MARK) 36, DA TA 3'7,
a DATA field 41 consisting of a CRC(2) 38;
They are arranged in the order of GAP(3) 39, and the number of bytes and data contents of each area are as shown in the figure. Write information is DAT
Written to A37.

Next, the case where write information is written together with initialization will be explained. When the FD8 is set to FDI)7 and commands for initialization and information writing are given from the keyboard 2, the CPU 3 reads the FDI via the CPU interface 5 based on the control program in the ROM4.
First, a restore command is sent to DC6.

When the store command is sent to the F'DC6 or is loaded into the command register 16, and a control signal is sent from the FDC6 to the FDD7, the head of the FDD7 moves to the outside of the FDI3, and when the head moves to the outermost position. , a detection signal is sent from the FDD 7 to the FDC 6, and (00) is set in the track register 17. Track 22 of the FD 8 corresponding to the position of the head outside this is set as track number (00).

Next, the CPU 3 sends a write track command to the FDC 6 via the interface 5. The write track command sent to the FDC 6 is loaded into the command register 16. Further, the CPU 3 sends the initialization data to the FDC 6 according to the data format shown in FIG.
YNC(1) 27..., 5YNC(2) of sector section 24
)30, AM(1)31,... in order, and AM(2
) 36, write information is sent to the area DATA37.

These data and write information are stored in data register 1.
5 and sent from the data register 15 to the data shift register 14 as parallel data of 8 bits each. The data sent to the data shift register 14 is converted from the data shift register 14 into a serial signal, and is transferred to the FDC via the write information signal line (WD) 10.
7 and written to track 22 with track number (00). This means that write information has been written to the FD8 at the same time as the data format is initialized.

In other words, when initializing the FD8, DATA37 is
Write information is included in the area to form a data format. The information to be written to DATA37 is stored in RAM4 in advance.
It can be prepared in advance or obtained by other means as appropriate.

In addition, when forming 26 sector parts 24 in order, FDC
By sequentially setting numbers in the sector registers 18 of 6, the same operation as described above can be performed.

Also, when forming a data format in order on the tracks 22 with track number (00) and below, load the step command into the command register 16 of the FDC 6, move the head inward, and set the numbers in the track register 17 in order. You can do the same.

Further, when reading information from the FD 8 or writing information to the FD 8, a normal read or write operation can be overridden by using a read data or write data command.

(Effects of the Invention) As described above, the present invention initializes the FD and writes information at the same time, so it takes at least half the time compared to the conventional method that requires two steps of initialization and information writing. It has the advantage of being able to process data, and in particular, has the extremely significant effect of significantly shortening the time when forming data formats and writing information to a large amount of FDs.

[Brief explanation of the drawing]

The figures show one embodiment of the present invention, in which Fig. 1 is a block diagram showing the basic electrical configuration, Fig. 2 is a partial block diagram, and Fig. 3 is a block diagram showing the structure of the FDC. FIG. 4 is an explanation showing an example of data and tough format in the case of single density. 3...CPU 6...FDC7...FDC8
...FD

Claims (1)

[Scope of Claims] A magnetic disk drive device that reads from and writes to a magnetic disk, means for controlling the magnetic disk drive device to initialize the magnetic disk, and means for including write information in initialization data forming a data format. 1. A magnetic disk control device comprising: a magnetic disk controller configured to initialize a magnetic disk and write write information at the same time.