JPS6140635A - Magnetic disc controller - Google Patents

Abstract

PURPOSE:To shorten considerably the processing time of a magnetic disc FD by writing write information on the FD simultaneously with formation of a data format on the FD. CONSTITUTION:Format data of track number 00 of a master magnetic disc M- FD13 is stored in a format data storage area 15-1 of a memory buffer RAM. Format data of track number 02 is stored newly in the same format data storage area. Meanwhile, format data of track number 01 is stored in a format data storage area 15-2. In an operation step at this time, format data of track number 01 stored in the storage area 15-2 is written on a copy magnetic disc C-FD14. In case that another format data is stored in the storage area where format data is already stored in this manner, data is written after confirming whether already stored format data is all written on the C-FD14 or not.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a magnetic disk control device that writes format data to a magnetic disk (hereinafter referred to as FDD) such as a flexible disk cartridge.

(Prior art) Conventionally, in order to write information such as data and programs to an FD, two processing steps are required: first, initializing the FD to form a 7-ohm format, and then writing information according to the 7-ohm format after the snow has fallen. there were. When writing information to a new FD that does not have a 7-ohm format, or when writing information to an FD that has a different format of 7-ohm
D and F whose 7-ohmatsu was destroyed by electrical damage.
D,,i,; When re-formatting and writing information, several minutes of processing time was required.

1 In particular, with the spread of office computers, personal computers, etc., many software products are sold using FDs as media, and a large number of copy FDs are produced from master FDs.It is now possible to improve productivity by reducing FD processing time as much as possible. It was hoped that this would improve.

(Problems to be Solved by the Invention) An object of the present invention is to write write information at the same time when forming a data format on an FD,
The purpose is to significantly shorten the FD processing time.

In order to achieve the above object, this invention provides a master F.
Format data for each track including write information is read out from D to the data area and stored, and the format data of the stored tracks is sequentially written to the copy FD, in a processing time equivalent to the process of initializing a conventional FDj. The FD is characterized in that a 7-ohm format including write information is formed on the FD.

(Embodiment) FIG. 1 is a block diagram of a magnetic disk control device 1 according to an embodiment of the present invention. A keyboard 4, a display device (CRT > 5, ml) are connected to the bus 3 connected to the CPU 2.
l wave device ROM) 6, memory buffer (RAM)? , C
A PU interface 8 is connected. A reading magnetic disk controller (hereinafter referred to as R-FDC) 9 and a writing magnetic disk controller (hereinafter referred to as W-FDC) 10 are connected to the CPU interface 8. A magnetic disk drive device (hereinafter abbreviated as R=F, I)D) 11 is connected, and a write magnetic disk drive device (hereinafter abbreviated as W-FDD) 12 is connected to the W-FDCIO.

The R-FDDII is controlled by the R-FDC9 and is a master magnetic disk (hereinafter abbreviated as M-FD) 1.
It functions as a format data reading means for reading the format data of No. 3.

The W-FDD 12 is a copy magnetic disk (hereinafter abbreviated as C-FD) 1 under the control of the W-FDCIO.
It functions as a format data writing means for 4.

The memory buffer y (RAM") 7 functions as a format data storage means for temporarily storing the format data read from the M-FD 13, and is a format data storage area that stores at least one track or more of format data. and the right, which has an information storage area for storing other information.

A storage device (ROM) 6 stores a control program for the magnetic disk control device 1 shown in FIG.

The display device (CRT) 5 displays information indicating the control state of the magnetic disk controller 1, commands from the keyboard 4, information, and the like.

The CPU 2 functions as a control processing means by executing a control program shown in FIG. 6, which will be described later, and includes a storage control function of a memory buffer 7 (RAM) 7.

# & 2 diagram shows CPU 2, CPU interface 8, R
-FDC9 and W-FDCIOlR-FDDll and W-F
Figure 3 shows the transmission relationship between DD I2 and R-FDC.
9, shows a block diagram of W-FDCI O.

FIG. 4 diagrammatically shows the storage area of the memory buffer (RA'M) 7, showing a format data storage area 15 and an information storage area 16.

FIG. 5 diagrammatically shows an example of format data.

Next, referring to FIGS. 1 to 5, the configuration of the present invention will be explained in more detail.
FDC9 and W-FDCIO'11] are bidirectional data access lines (D, ~D,)1 consisting of 8 bits.
7' and read from R-FDC9 7
The automatic data and the format data written to the w-FDc9 are transferred to the CPU digitizer 7 as parallel data.
Transmission is carried out with Ace 8.

The '7 format data read from the M-FD 13 is read out from the R-FDD 11 as a serial signal and sent to the R-FD by the read information signal line (RAWREAD) 1B.
The format data sent to D9 and written to C-FDl4 is sent as a serial signal to the write information signal line (
W-FDD12 from W-FDCIO by WD)19
sent to.

Both the R-FDD 9 and the W-FDCIO have the same configuration and have a reading or writing function according to instructions from the CPU side, and will be described with reference to the block diagram shown in FIG. 3.

The data output rose 7720 is a buffer that connects format data etc. read from the R-FDDll to the bidirectional data access lines (D0 to D,) 17.

The data shift register (DSR) 21 is an 8-bit serial shift register, and in the R-FDD9, the R-FD
Read format data from DII to W-FD
The CIO temporarily stores the write format data from the CPU interface 8 as serial data.

The data register (DR) 22 is an 8-bit parallel register, and in the R-FDD9, the data shift register (DR) 22 is an 8-bit parallel register.
8-bit parallel data is sent from the DSR) 21 to the data register (DR) 22, and in the W-FDCIO, the data loaded from the bidirectional access line (D, to D7) 17 to the data register 22 is shifted in parallel. It is sent to the register (DSR) 21.

The command register (OR) 23 is an 8-bit register, and commands are sent to the command register 23 from the CPU side according to the operation desired to be executed by the R-FDD il and W-FDD 12. The main commands and an overview of their operations are shown below.

(Command) (Command operation overview) Restore... Move the head to track (00) of Fj) Seek... Move the head to the specified track Step out... Move the head outside the FD 1 Move by one track Step in... Move the head inside the FD by one track Read data... Read the format data of the FD Write data... Write the format data to the FD Read ( Read) Address: Read track that reads the ID field of the FD...Write track that reads all the data for one track of the FD...Sector register (that writes the data for one track of the FD) SCR) 24 is an 8-bit shift register, and in read data and write data commands, the target sector number is written prior to execution of the instruction.

CRC (Cyclic Redundancy)
ck) The circuit 25 checks whether there is any erroneous writing or erroneous reading in the serial pit cell (16-bit data) transferred between the FD and the FD. W-FD
The CIO automatically generates CRC data from the write format data to C-FDl and 4, and writes the CRC data to the W-FDCIO. In R-FDD9, C-F
When reading from D14, CRC data is reproduced from the serial bit cell (16 bit data) of the read format data and an error check is performed.

The arithmetic circuit (ALU) 26 compares serial data, increments) (+1), increments] (-1)
, through (+0) functions, and performs operations such as updating the contents of each register, checking with the register, and comparing the magnitude. The status register (STR) 27 is an 8-bit register, and its contents change depending on the type of command that has already been sent to the command register 23 and is being executed. Therefore, the status can be known from the CPU side.
Status register (STR)
By reading the contents of 27, R-FDD9, W7
Content status of FD10 and R-FRD11, W-FDD1
The track register (TR) 48 is an 8-bit register and is normally used to hold the track number at the head position of the FDD. The above data register (DR) 22, command register (CR)
) 23, sector register (SCR) 24, status register (STR) 27, track register (TR) 48
is selected and designated from the CPU side via a selection designation signal line (not shown), and reading and writing (loading) are performed.

FIG. 5 diagrammatically shows an example of format data stored in M-FC12, and the illustrated example shows the case of single density (FM).

The track 28 includes a preamble section 29, 26 sector sections 30, and a post-preamble section 31. Preamble part 29 is GAP (0) 32.5 YNC (1) 33
, IDM (INDEX MARK) 34, GAP (1)
The number of bytes and data contents of each area are as shown in the figure. Note that the data is expressed in hexadecimal numbers, and the symbol * indicates that there is a missing clock. Sector part 30 is 5YNC (2) 36, AM (1)
(ID ADDRESS MARK)37, ID38,
ID field 40 consisting of CRC(1) 39 and GA
P(2)41, 5YNC(3)42, AM(2)(D
ATAMARK)43. DATA44. CRC(2)4
DATA field 46 consisting of 5 and GAP (3) 4
The number of bytes and data contents of each area are as shown in the figure. Therefore, the format data in the present invention represents all data from the preamble section 29 to the postamble section 31. CRC(
1) 39 is a CRC when writing format data.
The ID field 40 is created by the circuit 25.
Considering the bit string from the first bit of AM(1)37 to the last bit of the data of ID38 as a binary polynomial,
Divide this polynomial by a specific binary polynomial and use the remainder as C
It is written continuously as RC(1)39 after the data of ID38. Similarly, AM in DATA field 46
(2) The bit string from the first bit of DATA 43 to the last bit of DATA 44 is converted into a specific binary polynomial, crab 1, etc. Surplus. . . (2) Continuously written after 44Ml-CDATA44. "Symbols shown in Figure 5 (a),
(b) indicates CRC, and (c) indicates ID data, ie, address, sector capacity, etc.

FIG. 6 is a flow chart showing the specific operation of the present invention, and FIG. 7 is a flow chart showing the specific operation of the present invention, and FIG.
FIG. 4 is an explanatory diagram illustrating the transmission relationship of format data to FCl4.

Next, the specific operation of this embodiment will be explained with reference to FIGS. 6 and 7.

M-FCl2 to R-FDD 11, C-FCl4 to W
-FDCI2 and issue a command from the keyboard 4, the CPU 2 sends a restore command to the W-FDCIO via the CPU interface 8 in step S1. The store command sent to W-FDClo is loaded into the command register (CR) 23, and the store command is sent to W-FDClo.
A control signal is sent from DCIO to W-FDDII, and W-
The FDDII head (not shown) moves outward.

W-FDDII has a limit switch (
) is provided, and when the head moves and the limit switch is activated, the head stops, and the limit switch switches the W-FDDII to W-FDC.
A detection signal is issued to the IO, and the track register of the W-FD CIO.

(TR) 48 is set to (00) as the track number. This means that the head position of C-FC14 is set to track number (00) in W-FDCI2.

When the track number is set to (00) in the track register (TR) 48 of the W-FDCIO, the W-FDCIO
from the CPU2 to the track register (TR) 48 (00
) is set is sent to crtr2. When the CPU 2 determines in step S2 that there is confirmation information, the R-
'A read address command is sent to the command register (CR) 23 of the FDC9.

When the read address command is loaded into the command register (-CR) 23, the ID3B of the track 28 corresponding to the head position is read out by the R-FDDll under control from the R,-FI)C9. The track number read from ID3B is track register (TR)
48, and this track number is sent to the CPU 2.

In step S4, it is determined whether the track number sent from the R-FDC 9 is (00) or not.

If the track number sent is not (00), the command register (,
A step-out signal is sent to CR) 23. R-F
DC9ノ: ] v > When a step-out command is loaded into the drain (CR) 23, the head of the R-FDD 11 is moved to the outside of the M-FD 13 by one track under the control of the R-FDC 9. When the head moves outward, the step signal from R-FDDII becomes R-FDC9.
is sent to CPU2 via. In step S7, it is determined whether or not there is a step signal, and if there is no step signal, the command register (C
A step-out signal is sent to R) 23. If there is a step signal, step S3 is executed and the head is
Similar operations are repeated until the track number (00) of the FD 13 is reached.

When it is determined in step S4 that the head of R-FDDII is at the position of track number (00), step S7
Proceed to. In step S7, a read track command is sent to the command register (CR) 23 of the R-FDC 9.

When the read track command is loaded into the command register (CR) 23 of the R-FDC9, the R-FDD1. ,,1 by M-F
All data of the data 7 format of the track number (00) of D13 is read out. The format data from the R-FDDll is stored in the format data storage area 15-1 of the memory buffer 7 in step S7.

Next, in step S8, it is determined whether all the format data of the track number (00) has been written.

That is, in the data 7 format shown in FIG. 5, it is determined whether the data up to the post-ampule section 31 at the end of the track 28 has been stored. When all the format data of the track number (00) is stored in the memory buffer 7, the process advances to step S9. In step S9, R
- A step-in command is sent to the command register (CR) 23 of the FDC 9.

When the step-in command is loaded into the command register (CR) 23 of the R-FDC 9, the head of the R-FDD 11 is set to M for one track under the control of the R-FDC 9.
-Move inside FD13.

When the head moves by one track, a step signal is sent from the R-FDDll to the CPU 2 via the R-FDC9. In step 310, it is determined whether or not there is a step signal, and if there is no step signal, the R-FD
A step-in command is sent to the command register (CR) 23 of C9.

If there is a step signal, the process advances to step Sll.

In step Sli, command register x of R-FDC9
(CR)23G=Read address command is sent. When the read address command is loaded into the command register (CR) 23 of the R-FDC9, the R-FDC? R-FDD under the control of
D38 is read.

The track number read from ID38 is loaded into track register (TR) 4B, and this track number is
Sent to PU2. This track number is (01) because it was moved inward by one track in step S9, but
In step S12, it is determined whether the last track number is the last track number (76). C.P.
The track number sent to U2 is the last number (76)
If so, end, otherwise proceed to step 31.3. In step S13, a read address command is sent to the command register (CR) 23 of the R-FDC 9. R-FDC9 command register (CR)
When the lead track command is loaded into 23, 'R
= M7F by R-FDDII under the control of FpC9
D13 track number (01) data 7o, -
All data on the mat is read. R, -FDDl
The format data from 1 is stored in the 7-ohm data storage area 15- of the memory buffer 7 in step S14.
2 is stored. In this way, by storing one track's worth of format data in the format data storage area 15-1 of the memory buffer 7 and starting to store one more track's worth of format data, the C-FD1
You can now prepare to write format data to 4.

Next, in step S15, a write track command is sent to the command register (CR) 23 of the W-FDCIO. In step S16, the format data stored in the 7th to 1i areas 15-1 of the memory buffer 7 is sent to the data register (DR) 22 of the W-FDCIO in 8-bit units. The format data stored in the format data storage area 15-1 at this time is the format data of the track number (00) of the M-FD 13. The format data sent to the data register (DR) 22 is sent as a serial signal from the data shift register (DSR) 21 to RAWREAD.
line 18 to W-FDD 12 and C-FD 14
will be written to. At this time, the head position of the W-FDD 12 has already been determined by Stella 7S1 and step S2.
Since it is located at the outermost side of the FD 14, the format data of the track number (00) of the M-FD 13 will be written to the outside III of the C-FD 14. In step S17, the format data storage area 15 of the memory buffer 7 -1 data all C-FD14
It is determined whether or not it has been written to. When it is determined that all the format data in the format data storage area 15-1 has been written, in step 818, the format data storage area 15-2 of the memory buffer 7 is written.
It is determined whether all the format data of the track number (01) of the M-FD 13 has been stored. When it is determined that all the format data of the track number (01) has been written to the format data storage area 15-2 of the memory buffer 7, the process advances to step S19.

In step S19, a step-in command is sent to the command register (CR) 23 of the RF'DC9. When the step-in command is loaded into the command register (OR) 23 of R-FDC9, the head of R-FDDII moves by one track under the control of R-FDC9, and the step signal from R-FDDll is transferred to R-FDC9.
9 to CPU2. In step S20, it is determined whether or not there is a step signal, and if there is no step signal, the command register (C
A step-in signal is sent to R) 23. If there is a step signal, the process advances to step 821.

In step S21, a read address command is sent to the command register (CR) 23 of the R-FDC 9.

When the read address command is loaded into the command register (CR) 23 of the R-FDC9, the ID3 of the track 28 is read by the R-FDDll under the control of the R-FDC9.
8 is read out. The track number read from the ID 38 is loaded into a track register (TR) 48, and this track number is sent to the CPU 2. This trough number is (02) because it has moved inward by one track in step S19, but it is determined in Stella 7'S22 whether the track number is the last track number (76).

The track number sent to CPU2 is the last number (7
6), the process ends; otherwise, the process proceeds to step 323.

In step S23, a read track command is sent to the command register (CR) 23 of the R-FDC 9.

When the read track command is loaded into the command register (CR) 23 of the R-FDC9, all data in the data 7-orbit of the track number (02) of the M-FD13 is read out by the R-FDDll under the control of the R-FDC9. . The format data " from R-FDDll is stored in the format data storage area 15-1 of the memory buffer 7 in step S24.

The format data storage area 15-1 stores format data for track number (00).
Since it has already been confirmed in step S17 that all the data in the format data storage area 15-1 has been written to the C-FD 14, the data 7-ormat with track number "02" is written in the format data storage area 15-1. There is no problem even if you write a new one.

Next, in step S25, a step-in command is sent to the command register (CR) 23 of the W-FDCIO. When the step-in command of the W-FDCIO command register (CR) 23 is loaded, the W-FDCl
From the control school of o, the head of W-FDC12 moves by one track, and the step signal from W-FDC12 becomes W-
It is sent to CPU2 via FDCIO. Step S2
In step 6, it is determined whether or not there is a step signal, and if there is no step signal, a step-in command is sent to the command register (CR) 23 of the W-FDCIO again. If there is a step signal, the process advances to step S27.

In step S27, a write track command is sent to the command register (CR) 23 of the W-FDCIO. Next, in step 82B, the format data stored in the format data storage area 15-2 of the memory buffer 7 is sent to the data register (DR) 22 of W-FDClo in 8-bit units. The 7-orbit data stored in the format data storage area 15-2 at this time is the format data of the track number (01) of the M-FD 13. Data register (DR) 2
The 7 format 1 data sent to the W-FDC 12 is written to the C-FD 14 by the W-FDC 12.

FIG. 7 shows the flow of 7-sized data at step 828.The track number (00 ) is written, and in step S24, the format data of the track number (0?) shown by the arrow TO2 is newly written in the same storage area 15-1.On the other hand, Omatsu)?'-9□.15-2 e l!
), -/98 g(. Data is written to C-FD 14.

In the present invention, as shown in step 818, if data is to be newly stored in the format data storage area 15 in which format data has already been stored, the procedure described above is performed. All of the formatted data is written to C-FD14.
′2 “°”°, is there.

Furthermore, even when reading the format data storage area 15 and writing it to the C-FD 14, it is necessary to check whether all the format data of one track is stored in the 7-ohm MatsuF data storage area 15. Nade・
``-Performs evening writing and writing.'' (Effects of the invention) Since this invention has the above-described configuration and operation, it is possible to write write information at the same time as forming a data format on an FD. Therefore, it has an extremely significant effect of significantly shortening the FD processing time.

[Brief explanation of the drawing]

The figures show one embodiment of the present invention, in which Fig. 1 is a block diagram, Fig. 2 is a block diagram showing the data transmission relationship, Fig. 3 is a block diagram of R-FDC9 and W-FDClo, and Fig. 4 is a block diagram showing the data transmission relationship. The figure is an explanatory diagram schematically showing the storage area of the memory buffer y (RAM) 7, FIG. 5 is an explanatory diagram showing an example of format data, FIG. 6 is a flowchart showing specific operations, and FIG.
It is an explanatory diagram showing a flow of an Omatsu toter. 1...Magnetic disk control device 2...CPU
7...Memory buffer 7 (RAM) 9...R
-FDC10...W-FDCll...R-FDD
12...W-FDC13...M-FD 14
...C-FD15...7 automatic data storage area patent, patent applicant Sword Co., Ltd. Procedural amendment (method) December 24, 1980

Claims (2)

[Claims] (1) Format data reading means for reading format data of a master magnetic disk; format data storage means for storing at least one track of format data from the format data reading means; and a copying magnetic disk. a format data writing means for writing format data to the magnetic disk for copying, and a control processing means for sending the format data read from the format data storage means to the format data writing means and writing the format data to the magnetic disk for copying. Magnetic disk control device. (2) The control processing means includes storage control means for newly storing format data of a different track of the master magnetic disk in a format data storage area that has already been read from the format data storage means. A magnetic disk control device according to scope (1).