JPS6139753A - Fsk signal demodulator - Google Patents

Abstract

PURPOSE:To perform demodulation with fast responsiveness by providing a delay means which delays an FSK signal by one or half period of two kinds of frequencies and generates two kinds of delay signals and an arithmetic means which compares the difference between or sum of two kinds of delay signal with the FSK signal. CONSTITUTION:The FSK signal is inputted to a mark period delay circuit 2 and a space period delay circuit 3 to obtain signals which are delayed by one period of their frequencies. The output signal of the mark period delay circuit 2 is inputted to a subtracting circuit 4. The subtracting circuit 4 inputs the FSK signal directly and subtracts the former from the latter and inputs its result to an absolute value circuit 5 and the absolute value of the subtraction result of the subtracting circuit 4 is inputted to a subtracting circuit 6. A discriminating and demodulating circuit 9 easily decides the sign and performs modulation and outputs the result to an output terminal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to an improvement of an F8 signal demodulator that demodulates an FSK signal consisting of two types of frequency waveform sequences frequency-modulated by a binary signal.

(Background of the Invention) Conventionally, as a method for demodulating an FSk signal consisting of two types of frequency waveform sequences and determining the sign of the signal, a method using two filters has generally been used. This is done by installing a filter that passes only the frequency of the manic signal and a railter that passes only the frequency of the space signal, and inputs the received signal to each of the two filters. Signal demodulation is performed by comparing the outputs of the filters with a comparator.

However, with this method, if the frequency deviation between the mark signal and the space signal is small, high performance is required for the second filter in order to perform accurate demodulation, which causes problems in terms of manufacturing technology, cost, shape, etc. arise. Furthermore, since distortion occurs in the rise of the filter, there is also the drawback that the response is slow. Another method for demodulating FSK signals is the simultaneous detection method. This is a method in which an oscillator emits a signal with a frequency of either mark 1 or space signal, and demodulation is performed using the signal obtained by subtracting it from the received signal. It is necessary to synchronize the oscillation signal from the oscillator with the received signal, and the circuit for this is complicated, which also requires manufacturing technology,
There are problems in terms of cost and shape. □ - (Objective of the Invention) The aim of the present invention is to solve the above-mentioned problems and provide an FSK signal demodulator that can perform demodulation with fast response using a simple circuit that does not use a filter. .

(Features of the Invention) In order to achieve the above object, the present invention provides two types of delayed signals by delaying an FSK signal consisting of two types of frequency waveform series by one period or a half period of the two types of frequencies. and a calculating means for comparing the absolute value of the difference or sum between the FSK signal and the two types of delayed signals, and demodulating the binary signal based on the comparison result of the calculating means. It is characterized by the following.

(Embodiments of the Invention) Hereinafter, the present invention will be described in detail based on illustrated embodiments.

FIG. 1 is a block diagram showing one embodiment of the present invention. First, an FSK signal consisting of two types of frequency waveform series is input to the input terminal 1. E (11)
It is expressed by the following formula.

The FSK signal with (A: signal amplitude, ω,: mark signal angular frequency, ω8 space signal, minute angular frequency) is input to the mark period delay circuit 2 and the space period delay circuit 3, and one period of each frequency is input. The signals Em(t) and Es(t) are delayed by . These are expressed as follows.

EM(t)=EFII(t-rM)
(2) Es(t) = Eyll (t-1g)
(a) (τ = 2π/ω1.τ8
=2π/ω,) Signal E output from the mark period delay circuit 2.

(tl is input to the subtraction circuit 4. The FSK signal Eys(t) is separately input to the subtraction circuit 4, and here, FS
The signal Eu(tl) is subtracted from the K signal Eyg(t), and the result is further input to the absolute value circuit 5, and the absolute value of the subtraction result by the subtraction circuit 4 is input to the subtraction circuit 6. In exactly the same way, 1, The signal EII(t) output from the space period delay circuit 3 is input to the subtraction circuit 7, and the signal EII(t) is inputted to the subtraction circuit 7.
The signal Ell(t) is subtracted from the SK signal Er5(t), the result is input to the absolute value circuit 8, and the absolute value of the subtraction result is input to the subtraction circuit 6.

Output signal of absolute value circuit 5.8 & (t) , & (t
) is the following formula % formula % The subtraction circuit 6 performs a subtraction process expressed by the following formula.

E (t) = El (t) - Et (t) = lEr
s(1-EM(t)I-, IEys(t)-Ee(t)
I (6), subtraction times l! The output signal (1) of No. 6 is input to the discrimination demodulation circuit 9, and in the discrimination demodulation circuit 9, the signal E(t
) determines the sign of the FSK signal EFII (t).

The relationship between the polarity of the signal E(t) and the sign of the FSK signal Eys(t) is as follows from equations (1), (2), and (3).

(1) When FSK signal Ea, (t) is a mark signal.

E(1””I As1vG)yt-As1nω5(t
-rM)1-l As1IIωat-Asin(dM(
t Tm ) l≦0(7) (n) FSK signal EFII (when l is a space signal.

E (tl ”' l As1nωat As1nω5
(t-ty)l-l As1a (t)m t -As
in 6)m (−τ,)1≧0(8) (7) As shown in equations (8), if the signal E(t) is negative, then the FSK signal E? II (tl is mark, signal E (
If t) is positive, it is a space, so if this fact is used, code discrimination demodulation is easily performed in the discrimination demodulation circuit 9, and the result is outputted to the output terminal 10.

Note that if a value obtained by integrating the value of the signal B(t) over a certain period of time is used for discrimination demodulation, the reliability and stability of discrimination will increase.

In the present invention, it is necessary to delay the signal, but this can be easily done by sampling the signal at a constant cycle and storing the value in analog or digital form. . When storing the sampling values and performing the subsequent arithmetic processing digitally, the use of a microcomputer or the like has the additional advantage that the device can be made smaller. FIG. 2 shows another embodiment of the present invention in which digital processing is performed in this manner. The same parts as in FIG. 1 are designated by the same reference numerals.

The signal delay method according to the present invention will be explained based on the embodiment shown in FIG. The sampling period generation circuit 11 outputs the sampling signal EIIF to the A/D conversion circuit 12 at periods τ and P. Here, the sampling period τ, P
is determined as follows to conveniently delay the FSK signal Eyg (t) by one mark signal period τ and one space signal period τ8.

τ. =-τM(9) ,,-n(II (m, n are integers) When defined in this way, the signal values one period before each of the mark signal and space signal are both equal to the sampling period τ, P. It is possible to directly use the signal value sampled an integer multiple earlier.The signal value E one period before each period of the mark signal and space signal.
m(tl, Ell(1)) is expressed by the following formula.

EM(i) = Era(tTM) = Ey
g (t m Tap ) Qυ & (tl=Er
g (t ”m) = EFI (t nTgp
) FSK signal E□(
tl is input to the A/D conversion circuit 12 and converted into a digital signal. The sampling signal EIlp is input to the A/D conversion circuit 12 from the sampling period generation circuit 11 with a period τ8P, and the A/D conversion circuit 12 generates the FSK signal Eys(t) according to this sampling signal E.
The sampling value is output to the memory circuit 13 and the calculation/discrimination circuit/prefecture 4. The storage circuit 13 temporarily stores this sampling value, which is an integral multiple of the sampling period τ8P. The signal is outputted to the operation determination circuit 14 after one period of mark signal period .tau. and space signal period .tau.8. That is, the operation determination circuit 14 receives the FSK signal Ea, (t) from the A/D conversion circuit 12, and the signals E, t(t), and Es(tl) from the storage circuit 13. □Therefore, In the arithmetic discrimination circuit 14, the formula (6)
The calculation represented by is performed, and from the polarity of the signal E(t), FS
The K signal EF8 (t) is demodulated and the result is output to the output terminal 10.

(Correspondence between the invention and the embodiments) In the embodiment shown in FIG. 1, the mark signal delay circuit 2 and the space signal delay circuit 3 are replaced by the delay means of the present invention, and the subtraction circuits 4, 6.7 and the absolute value circuits 5.8 correspond to the calculation means of the present invention, respectively.

(Modification) In the above explanation, the FSK signal Ern(t
) is delayed by one period each of the mark signal period - and the space signal period τ8, but,
Demodulation can be performed in the same way even if the signal is delayed by a half period of each of the mark signal period - and the space □ signal period τ. In this case, the signal EM (t) delayed by half a period
, El (t) is as follows.

EM(1=EFI(t)
(2) Determination of the sign of the FSK signal EN (t) is performed using the FS
K signal EFI (tl and delayed signal - I EM(t)
, & (t) by comparing the absolute values of the sums. This can be expressed as follows.

E(t) = l En(t)+8m(t) l-I
En(t) + Es(t) + (6)'EFI (t
) is a mark signal: E(t)≦OEm(t) is a space signal: E(t)≧0 In this case, the sampling period τ
, P are defined as follows.

τIIF=τw72m (
9)'τ, P=τs/2rL(tl') (Effect of the invention) As explained above, according to the present invention, an FSK signal consisting of two types of frequency waveform sequences is converted into one cycle of the two types of frequencies. Alternatively, a delay means for forming two types of delayed signals by delaying the FSK signal by half a cycle, and a calculating means for comparing the absolute value of the difference or sum between the FSK signal and the two types of delayed signals, Since the binary signal is demodulated based on the comparison result of the arithmetic means, it is possible to perform demodulation with quick response using a simple circuit that does not use a filter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention when digital processing is performed. 2... Mark cycle delay circuit, 3... Space cycle delay circuit, 4, 6.7... Subtraction circuit, 5.8... Absolute value circuit, 9... Discrimination demodulation circuit, 11...・Sampling cycle generation circuit, 12・-A/D conversion circuit, 13...
Memory circuit, 14... operation discrimination circuit. Patent applicant Osaki Electric Industry Co., Ltd. Agent Minoru Nakamura

Claims (1)

[Claims] 1. In an FSK signal demodulator that demodulates an FSK signal consisting of two types of frequency waveform sequences frequency-modulated by a binary signal, by delaying the FSK signal by one period or a half period of the two types of frequencies. An FSK signal demodulator, comprising: a delay means for forming two types of delayed signals; and an arithmetic means for comparing the absolute value of the difference or sum between the FSK signal and the two types of delayed signals.