JPS6138506B2 - - Google Patents

Info

Publication number
JPS6138506B2
JPS6138506B2 JP55105558A JP10555880A JPS6138506B2 JP S6138506 B2 JPS6138506 B2 JP S6138506B2 JP 55105558 A JP55105558 A JP 55105558A JP 10555880 A JP10555880 A JP 10555880A JP S6138506 B2 JPS6138506 B2 JP S6138506B2
Authority
JP
Japan
Prior art keywords
virtual machine
register
domain
address
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55105558A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5733477A (en
Inventor
Masayuki Ooya
Tsutomu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10555880A priority Critical patent/JPS5733477A/ja
Publication of JPS5733477A publication Critical patent/JPS5733477A/ja
Publication of JPS6138506B2 publication Critical patent/JPS6138506B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP10555880A 1980-07-31 1980-07-31 Computer system Granted JPS5733477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10555880A JPS5733477A (en) 1980-07-31 1980-07-31 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10555880A JPS5733477A (en) 1980-07-31 1980-07-31 Computer system

Publications (2)

Publication Number Publication Date
JPS5733477A JPS5733477A (en) 1982-02-23
JPS6138506B2 true JPS6138506B2 (enExample) 1986-08-29

Family

ID=14410870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10555880A Granted JPS5733477A (en) 1980-07-31 1980-07-31 Computer system

Country Status (1)

Country Link
JP (1) JPS5733477A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766352B2 (ja) * 1986-03-25 1995-07-19 株式会社日立製作所 仮想計算機システム

Also Published As

Publication number Publication date
JPS5733477A (en) 1982-02-23

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