JPS613600U - sample hold circuit - Google Patents
sample hold circuitInfo
- Publication number
- JPS613600U JPS613600U JP8707584U JP8707584U JPS613600U JP S613600 U JPS613600 U JP S613600U JP 8707584 U JP8707584 U JP 8707584U JP 8707584 U JP8707584 U JP 8707584U JP S613600 U JPS613600 U JP S613600U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- hold circuit
- sample hold
- gate circuit
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
ｒ．２図は第１図の回路の動作をあらわす信号説明図、
第３図は従来のサンプルホールド回路を示す図、第４図
は第３図の回路の動作をあらわす信号説明図、第５図は
第４図の信号の一部を示す説明図である。
Ｑｌ〜Ｑ４・・・トランジスタ、ｓｗ１，ｓｗ２・・・
スイッチ、ＣＡ， ＣＢ−・・コンデンサ、２０・・・
ゲート回路、２１・・・ダイオード。r. Figure 2 is a signal diagram showing the operation of the circuit in Figure 1;
3 is a diagram showing a conventional sample and hold circuit, FIG. 4 is an explanatory diagram of signals showing the operation of the circuit of FIG. 3, and FIG. 5 is an explanatory diagram showing a part of the signals of FIG. 4. Ql~Q4...transistor, sw1, sw2...
Switch, CA, CB-...Capacitor, 20...
Gate circuit, 21...diode.
Claims (1)
た電流を出力端子に流すゲート回路と、前記ゲート回路
の前記入力端子に接続された充か電用の第１のコンデン
サと、前記ゲート回路の正：．記出力端子に接続された
ホールド用の第２のコンデンサとを具備したサンプルホ
ールド回路において、 前記ゲート回路の入出力端子間に、前記入力端子から出
力端子方向へのみ電流を流す方向性電流回路を接続した
ことを特徴とするサンプルホールド回路。[Claims for Utility Model Registration] A gate circuit that causes a current corresponding to one voltage of an input terminal to flow through an output terminal when a switch is turned on, and a charging circuit connected to the input terminal of the gate circuit. 1 capacitor and the positive of the gate circuit:. A sample-and-hold circuit comprising a second capacitor for holding connected to an output terminal, and a directional current circuit that allows current to flow only from the input terminal to the output terminal between the input and output terminals of the gate circuit. A sample and hold circuit characterized in that it is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8707584U JPS613600U (en) | 1984-06-12 | 1984-06-12 | sample hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8707584U JPS613600U (en) | 1984-06-12 | 1984-06-12 | sample hold circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS613600U true JPS613600U (en) | 1986-01-10 |
| JPH039200Y2 JPH039200Y2 (en) | 1991-03-07 |
Family
ID=30638960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8707584U Granted JPS613600U (en) | 1984-06-12 | 1984-06-12 | sample hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS613600U (en) |
-
1984
- 1984-06-12 JP JP8707584U patent/JPS613600U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH039200Y2 (en) | 1991-03-07 |
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