JPS6135753B2 - - Google Patents

Info

Publication number
JPS6135753B2
JPS6135753B2 JP53094777A JP9477778A JPS6135753B2 JP S6135753 B2 JPS6135753 B2 JP S6135753B2 JP 53094777 A JP53094777 A JP 53094777A JP 9477778 A JP9477778 A JP 9477778A JP S6135753 B2 JPS6135753 B2 JP S6135753B2
Authority
JP
Japan
Prior art keywords
output
memory
correction
sensitivity
sensor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53094777A
Other languages
Japanese (ja)
Other versions
JPS5522130A (en
Inventor
Joji Tajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9477778A priority Critical patent/JPS5522130A/en
Publication of JPS5522130A publication Critical patent/JPS5522130A/en
Publication of JPS6135753B2 publication Critical patent/JPS6135753B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Description

【発明の詳細な説明】 本発明は、MOS又はCCDなどの一次元又は二
次元に素子が配列されており各画素を個別の素子
で受光し、電気信号に変換するシリコンタイプイ
メージセンサの各素子毎の感度などの不均一性を
デイジタル的に補正する装置に関するものであ
る。
Detailed Description of the Invention The present invention relates to each element of a silicon type image sensor, such as a MOS or CCD, in which elements are arranged in one or two dimensions, and each pixel receives light with an individual element and converts it into an electrical signal. This invention relates to a device that digitally corrects non-uniformity in sensitivity, etc.

従来画象の撮像には電子管タイプのものがひろ
く利用されているが、近年、半導体技術の進歩に
伴ない固体のイメージセンサが耐久性、及び集積
度などの利点によつて実用段階に入つている。し
かし、これらイメージセンサの特徴として一次元
又は二次元に配列された各素子が各画素を構成
し、その各素子が製造工程により必ずしも均一に
製造されないため暗電流及び感度に不均一性が現
われる欠点がある。第1図に35素子の一次元セン
サの出力信号例を示す。V0(t)は各素子tに
関する暗時出力であり、V1(t)は同じく明時
出力である。これは、各素子毎に暗電流及び明電
流がまちまちであることを示す。第2図に例とし
て、t1,t2,t3の3素子の入射光量Iと出力電圧
Vの関係を示す。即ちシリコンタイプのイメージ
センサに於いては、IとVの関係は線型ではある
がI=o(入射光なし)の場合の出力V0(t)、
及び感度を示す傾きが各素子毎に異なつている。
このような出力信号をA/D変換器を用いて例え
ば8ビツトのデイジタル信号に変換し、信号処理
を行う場合、可能なだけの情報を信号から得るた
めには第3図に示すような構成をとる必要があ
る。即ち、イメージセンサ2からの出力信号は増
巾器3、A/D変換器4を介し、デイジタル化さ
れたのち、センサ補正装置1により補正され、信
号処理装置5で利用される。6は駆動回路であ
る。このセンサ補正装置の最も一般的な構成は第
4図に示すようなものである。ここでセンサは
2048素子CCDとする。センサ補正装置1はメモ
リ装置12から成る。メモリ装置12は2048個の
補正テーブルの集まりと考えることができる。即
ち、各センサ素子について、1つの補正テーブル
が対応する。補正テーブルにはA/D変換器4か
らのデイジタル信号(8ビツトの値)に対する真
のレベル値(8ビツト)が記憶されており、デイ
ジタル信号がアドレス母線101に加えられるこ
とにより真の値が出力される。
Conventionally, electron tube type sensors have been widely used to capture images, but in recent years, with advances in semiconductor technology, solid-state image sensors have entered the practical stage due to their advantages such as durability and integration. There is. However, a characteristic of these image sensors is that each pixel is composed of elements arranged one-dimensionally or two-dimensionally, and each element is not necessarily manufactured uniformly during the manufacturing process, resulting in non-uniformity in dark current and sensitivity. There is. Figure 1 shows an example of the output signal of a 35-element one-dimensional sensor. V 0 (t) is the dark output for each element t, and V 1 (t) is the bright output as well. This indicates that the dark current and bright current are different for each element. As an example, FIG. 2 shows the relationship between the amount of incident light I and the output voltage V of three elements t 1 , t 2 , and t 3 . That is, in a silicon type image sensor, although the relationship between I and V is linear, the output V 0 (t) when I=o (no incident light),
And the slope indicating sensitivity differs for each element.
When converting such an output signal into, for example, an 8-bit digital signal using an A/D converter and performing signal processing, the configuration shown in Figure 3 is required to obtain as much information as possible from the signal. It is necessary to take That is, the output signal from the image sensor 2 is digitized via an amplifier 3 and an A/D converter 4, corrected by a sensor correction device 1, and used by a signal processing device 5. 6 is a drive circuit. The most common configuration of this sensor correction device is as shown in FIG. Here the sensor is
It is a 2048 element CCD. The sensor correction device 1 consists of a memory device 12 . The memory device 12 can be thought of as a collection of 2048 correction tables. That is, one correction table corresponds to each sensor element. The correction table stores the true level value (8 bits) for the digital signal (8 bit value) from the A/D converter 4, and the true value is determined by adding the digital signal to the address bus 101. Output.

各センサ素子は互いに異なる感度を持つている
可能性があるため、上記の補正テーブルは2048個
必要であり、各補正テーブルは現在アドレス母線
101に入力されている信号の元となつたセンサ
素子のアドレスを駆動回路6が与えることにより
選択される。補正テーブルが2048個あるため、補
正テーブル選択のためのアドレス母線102は11
ビツト必要である。補正結果は共通の出力線10
3上に出力され、信号処理装置5に送られる。
Since each sensor element may have a different sensitivity from each other, 2048 correction tables are required, and each correction table corresponds to the sensor element that is the source of the signal currently input to the address bus 101. The selection is made by the drive circuit 6 giving an address. Since there are 2048 correction tables, the number of address bus lines 102 for selecting correction tables is 11.
Bits are required. The correction result is the common output line 10
3 and sent to the signal processing device 5.

以上の構成のセンサ補正装置の場合、各補正テ
ーブルは入力の8ビツトに対応して256バイトの
容量を持ち、これが2048個必要なため、全体とし
て512kバイトのメモリ装置12が必要となる。
このように各々の素子の各々の値に対する補正値
をメモリ装置12に持てば完全に信号を補正する
ことができる。しかしこのためには、2048素子の
イメージセンサの信号の補正のために4メガビツ
トもの大容量のメモリ装置を必要とし、装置の価
格が異常に高くなる。
In the case of the sensor correction device having the above configuration, each correction table has a capacity of 256 bytes corresponding to 8 bits of input, and 2048 of these tables are required, so a total memory device 12 of 512 kbytes is required.
In this way, if the memory device 12 has correction values for each value of each element, the signal can be completely corrected. However, this requires a memory device with a large capacity of 4 megabits to correct the signals of the 2048-element image sensor, making the device extremely expensive.

本発明の目的は補正精度を保つたままこのメモ
リ装置の容量を削減し安価なセンサ補正装置を提
供することにある。
An object of the present invention is to provide an inexpensive sensor correction device that reduces the capacity of this memory device while maintaining correction accuracy.

本発明はシリコンタイプのイメージセンサの特
徴を生かし、各素子の暗信号レベルをあらかじめ
記憶する暗信号メモリと、センサ出力をA/D変
換した出力から前記暗信号メモリの出力を減算す
る減算回路と、各素子の感度をあらかじめ記憶す
る感度メモリと、前記感度メモリの出力によりア
ドレスされる補正メモリと、前記減算回路の出力
及び前記補正メモリの出力を乗算し補正結果を出
力する乗算回路とから構成され、センサ補正を実
行するものである。
The present invention takes advantage of the characteristics of a silicon type image sensor and includes a dark signal memory that stores the dark signal level of each element in advance, and a subtraction circuit that subtracts the output of the dark signal memory from the output obtained by A/D converting the sensor output. , consisting of a sensitivity memory that stores the sensitivity of each element in advance, a correction memory that is addressed by the output of the sensitivity memory, and a multiplication circuit that multiplies the output of the subtraction circuit and the output of the correction memory and outputs a correction result. and performs sensor correction.

以下に本発明の動作を第5図の実施例を参照し
て説明する。例としては前述と同様2048素子の
CCDの場合を考える。このCCDは各素子の暗時
出力が帯域の5%以下の値の不均一性を持ち、感
度も同じく5%以下の不均一性を持つとする。言
いかえるとA/D変換の出力は0〜255の値をと
るが、255の5%は12.75であるため、各素子の暗
時出力はV0(t)は例えば0〜13の14通の値し
かとらない。このとき飽和光量を与えた場合に
も、各素子の、暗時出力を含めた出力値が255を
超えないようにするには、高々242(=255−13)
を光量に比例する出力の最大値となるようにす
る。各素子の、飽和光量に対する比例部分の出力
値 V2(t)=V1(t)−V0(t) …(1) は、やはり高々5%以内の不均一性を持つので、
229〜242の14通りの値しかとらない。暗信号メモ
リ13は、各素子tに対するV0(t)を記憶し
ており、感度メモリ15は第(2)式により与えられ
る、各素子tに対するV2′(t)を記憶してい
る。V2′(t)は0〜13の値をとる。これは各素
子の感度の識別番号と考えることができる。そし
て、同じV2′(t)を持つ素子はすべて同じ感度
を持つので、感度は2048の全素子に亘つて14通り
のみ存在する。
The operation of the present invention will be explained below with reference to the embodiment shown in FIG. As an example, 2048 elements are used as described above.
Consider the case of CCD. It is assumed that this CCD has a non-uniformity in the dark output of each element of 5% or less of the band, and also has a non-uniformity in sensitivity of 5% or less. In other words, the output of A/D conversion takes values from 0 to 255, but 5% of 255 is 12.75, so the dark output of each element is V 0 (t), for example, 14 times from 0 to 13. It takes only the value. At this time, even if a saturated light amount is given, in order to prevent the output value of each element including the dark output from exceeding 255, it is necessary to use at most 242 (= 255 - 13).
to the maximum value of the output proportional to the amount of light. The output value V 2 (t) = V 1 (t) − V 0 (t) (1) of the proportional part to the saturated light amount of each element still has non-uniformity within 5% at most, so
It only takes 14 values from 229 to 242. The dark signal memory 13 stores V 0 (t) for each element t, and the sensitivity memory 15 stores V 2 '(t) for each element t given by equation (2). V 2 '(t) takes a value from 0 to 13. This can be thought of as an identification number for the sensitivity of each element. Since all elements having the same V 2 '(t) have the same sensitivity, there are only 14 different sensitivities among all 2048 elements.

V2′(t)=V2(t)−229 …(2) 減算回路14はA/D変換器の出力線101
(8ビツト)のデータから暗信号メモリ13の出
力線130上のデータ(4ビツト)を減算し、出
力は信号線140に出力される。暗信号メモリ1
3のアドレスはCCDのスキヤンに従つてアドレ
ス母線102によりスキヤンされる。この結果暗
電流の不均一性の補正が行われた。感度メモリ1
5は同様にアドレス母線102によりアクセスさ
れ各素子の感度に対して予め測定され、格納され
ている感度の識別番号V′2(t)が信号線150
に出力される。補正メモリ16は各感度に対する
入力、出力間の比例定数を記憶しており、感度は
信号線150によりアドレスされ選択される。選
択された感度に対する比例定数は信号線160に
出力され、乗算回路17により、信号線140の
値と乗算される。乗算回路17の出力は補正結果
であり、信号線103を介して本発明のセンサ補
正装置から出力される。各感度i(=V′2(t))
Zに対する比例定数Wiは式(3)のように補正メモ
リ16に記憶される。この値は通常、整数部1
桁、少数部8桁、計9ビツト持てば十分である。
V 2 ′(t)=V 2 (t)−229 …(2) The subtraction circuit 14 is connected to the output line 101 of the A/D converter.
The data (4 bits) on the output line 130 of the dark signal memory 13 is subtracted from the data (8 bits), and the output is output to the signal line 140. Dark signal memory 1
Address No. 3 is scanned by the address bus 102 in accordance with the CCD scan. As a result, the non-uniformity of dark current was corrected. Sensitivity memory 1
5 is similarly accessed by the address bus 102, and the sensitivity identification number V' 2 (t) which is previously measured and stored for the sensitivity of each element is connected to the signal line 150.
is output to. The correction memory 16 stores a proportionality constant between input and output for each sensitivity, and the sensitivity is addressed and selected by a signal line 150. The proportionality constant for the selected sensitivity is output to the signal line 160 and multiplied by the value on the signal line 140 by the multiplier circuit 17 . The output of the multiplication circuit 17 is a correction result, and is output from the sensor correction device of the present invention via the signal line 103. Each sensitivity i (=V′ 2 (t))
The proportionality constant Wi for Z is stored in the correction memory 16 as shown in equation (3). This value typically has an integer part of 1
It is sufficient to have a total of 9 bits, including digits and 8 digits for the decimal part.

W1=255/229+i …(3) (ここでi=0〜13) 入力電圧V2に対する補正結果V3は式(4)のよう
になる。
W 1 =255/229+i (3) (where i=0 to 13) The correction result V 3 for the input voltage V 2 is as shown in equation (4).

V3=W1・V2 …(4) 補正結果が入力V2に比例することはシリコン
タイプセンサの線型性を利用している。この結
果、出力信号は第4図の構成の場合とほとんど同
様の精度の補正結果となる。このとき使用された
メモリの容量は暗信号メモリ13に2048×4ビツ
ド、感度メモリ15に同じく2048×4ビツトであ
り、補正メモリ16のビツト数は14×9ビツトと
わずかであるので総計約16キロビツトである。そ
のためメモリ容量は第4図の構成に比較して約
250分の1になつており大幅な削減効果が得られ
装置の価格を低下させることができる。
V 3 = W 1 · V 2 (4) The fact that the correction result is proportional to the input V 2 takes advantage of the linearity of the silicon type sensor. As a result, the output signal becomes a correction result with almost the same accuracy as in the case of the configuration shown in FIG. The capacity of the memory used at this time was 2048 x 4 bits for the dark signal memory 13, 2048 x 4 bits for the sensitivity memory 15, and the number of bits for the correction memory 16 was only 14 x 9 bits, so the total was about 16 bits. It's kilobits. Therefore, the memory capacity is approximately
The amount is reduced to 1/250, resulting in a significant reduction effect and lowering the cost of the equipment.

以上の実施例では暗信号の各素子毎の不均一性
を補正するために暗信号メモリと減算回路を構成
に含んでいるが、今後CCDなどの製造技術、及
び駆動技術の進歩により暗信号の不均一性は無視
できる程小さくなる可能性があり、その場合には
上記暗信号メモリ、減算回路を構成に含まずにセ
ンサ補正装置を構成することができる。その結果
上の例の場合には更に8キロビツトのメモリの削
減が可能になる。
In the above embodiment, a dark signal memory and a subtraction circuit are included in the configuration in order to correct the non-uniformity of the dark signal for each element. There is a possibility that the non-uniformity becomes negligible, and in that case, the sensor correction device can be configured without including the dark signal memory and the subtraction circuit. As a result, in the above example, an additional 8 kilobits of memory can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明により補正の対象と
なるイメージセンサの入射光量と出力信号の説明
図、第3図は本発明のイメージセンサ系における
位置づけの説明図、第4図は一般的なセンサ補正
装置の説明図、第5図は本発明の実施例である。 なお図において、1は本発明のセンサ補正装
置、2はイメージセンサ、3は増幅器、4はA/
D変換器、5は信号処理装置、6は駆動回路、1
3は暗信号メモリ、14は減算回路、15は感度
メモリ、16は補正メモリ、17は乗算回路であ
る。
Figures 1 and 2 are illustrations of the amount of incident light and output signals of the image sensor to be corrected according to the present invention, Figure 3 is an illustration of the positioning in the image sensor system of the present invention, and Figure 4 is a general diagram. FIG. 5, which is an explanatory diagram of a sensor correction device, is an embodiment of the present invention. In the figure, 1 is a sensor correction device of the present invention, 2 is an image sensor, 3 is an amplifier, and 4 is an A/
D converter, 5 is a signal processing device, 6 is a drive circuit, 1
3 is a dark signal memory, 14 is a subtraction circuit, 15 is a sensitivity memory, 16 is a correction memory, and 17 is a multiplication circuit.

Claims (1)

【特許請求の範囲】 1 複数の素子から成るイメージセンサの各素子
の感度をあらかじめ記憶する感度メモリと、あら
かじめ各感度に対する入出力間の比例定数を記憶
し前記感度メモリの出力によりアドレスされる補
正メモリと、前記イメージセンサの出力信号を
A/D変換した出力及び前記補正メモリの出力を
乗算し補正結果を出力する乗算回路とから構成さ
れ、センサ補正を実行するセンサ補正装置。 2 複数の素子から成るイメージセンサの各素子
の暗信号レベルをあらかじめ記憶する暗信号メモ
リと、前記イメージセンサの出力信号をA/D変
換した出力から前記暗信号メモリの出力を減算す
る減算回路と、各素子の感度をあらかじめ記憶す
る感度メモリと、あらかじめ各感度に対する入出
力間の比例定数を記憶し、前記感度メモリの出力
によりアドレスされる補正メモリと、前記減算回
路の出力及び前記補正メモリの出力を乗算し補正
結果を出力する乗算回路とから構成され、センサ
補正を実行するセンサ補正装置。
[Claims] 1. A sensitivity memory that stores in advance the sensitivity of each element of an image sensor consisting of a plurality of elements, and a correction that stores in advance a proportionality constant between input and output for each sensitivity and is addressed by the output of the sensitivity memory. A sensor correction device configured of a memory and a multiplication circuit that multiplies an output obtained by A/D converting an output signal of the image sensor by an output of the correction memory and outputs a correction result, and performs sensor correction. 2. A dark signal memory that stores in advance the dark signal level of each element of an image sensor consisting of a plurality of elements, and a subtraction circuit that subtracts the output of the dark signal memory from the output obtained by A/D converting the output signal of the image sensor. , a sensitivity memory that stores the sensitivity of each element in advance, a correction memory that stores a proportional constant between input and output for each sensitivity in advance and is addressed by the output of the sensitivity memory, and an output of the subtraction circuit and the correction memory. A sensor correction device that performs sensor correction and includes a multiplication circuit that multiplies output and outputs a correction result.
JP9477778A 1978-08-02 1978-08-02 Compensator for sensor Granted JPS5522130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9477778A JPS5522130A (en) 1978-08-02 1978-08-02 Compensator for sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9477778A JPS5522130A (en) 1978-08-02 1978-08-02 Compensator for sensor

Publications (2)

Publication Number Publication Date
JPS5522130A JPS5522130A (en) 1980-02-16
JPS6135753B2 true JPS6135753B2 (en) 1986-08-14

Family

ID=14119517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9477778A Granted JPS5522130A (en) 1978-08-02 1978-08-02 Compensator for sensor

Country Status (1)

Country Link
JP (1) JPS5522130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0919873A (en) * 1992-09-11 1997-01-21 Uriyuu Seisaku Kk Impact wrench

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572174A (en) * 1980-06-06 1982-01-07 Nippon Steel Corp Compensation method of linear array output
JPS58135414A (en) * 1982-02-05 1983-08-12 Yokogawa Hokushin Electric Corp Temperature compensating method of nonlinear signal
JPH01317444A (en) * 1988-06-17 1989-12-22 Nippon Zeon Co Ltd Novel deodorant composition

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028937A (en) * 1973-07-16 1975-03-24
JPS50159216A (en) * 1974-06-12 1975-12-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028937A (en) * 1973-07-16 1975-03-24
JPS50159216A (en) * 1974-06-12 1975-12-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0919873A (en) * 1992-09-11 1997-01-21 Uriyuu Seisaku Kk Impact wrench

Also Published As

Publication number Publication date
JPS5522130A (en) 1980-02-16

Similar Documents

Publication Publication Date Title
US7196725B1 (en) Image reading apparatus and computer readable storage medium
JPH04219063A (en) Image reader
US7362355B1 (en) Digital CMOS image sensor incorporating a programmable multi-functional lookup table
US7825975B2 (en) Imaging array with improved dynamic range
KR100215150B1 (en) Gamma correction circuit
US6587145B1 (en) Image sensors generating digital signals from light integration processes
EP0710034B1 (en) Apparatus and method for image scanning using a sensor array
JP2000513518A (en) Calibration method and system for imaging device
JP3804113B2 (en) Solid-state imaging device
US20040189836A1 (en) System and method for compensating for noise in image information
JPS6135753B2 (en)
JPS6135751B2 (en)
JPS6135752B2 (en)
JPS616612A (en) Extracting method of af information
JPH0530350A (en) Solid-state image pickup device
WO1987006080A2 (en) Analog/digital converter apparatus for quantizing transmittance voltage signals
JPH03195177A (en) Picture reader
JPH0556356A (en) Signal processing circuit
JP3091084B2 (en) Signal processing circuit
US7224485B2 (en) Apparatus and method mapping a look-up table in an imaging system
US7495806B2 (en) System and method for compensating for noise in a captured image
JP4396023B2 (en) Solid-state imaging device and driving method thereof
JP4103901B2 (en) Solid-state imaging device
CN112492237B (en) Image sensor, transfer circuit and transfer method thereof
JP2516902B2 (en) Solid-state imaging device