JPS6135737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data collection control device, and more particularly to a data collection control device that selectively collects data based on a collection control information signal from a preceding data transmitter.

Conventionally, the data transmitter had a data selection function,
Only the necessary data was being sent to each data collection section. For this reason, when adding a data collection section or changing the collection timing, there is a problem in that the data transmission section is changed, which affects the entire device. Furthermore, when trying to go back and collect previous data, the data transmission section becomes complicated.

The present invention improves the above drawbacks and provides a disaster prevention system,
The objective is to provide a data collection control device that can be applied to measurement systems and process control systems.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The data collection control device of the present invention will be described below with reference to the drawings.

FIG. 1 is a principle diagram of an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram thereof. In the figure, 1 is a data collection control device, and this data collection control device is a data transmission unit that transmits data 2, and a plurality of data collection units ₃₁ to ₃₃ having a function of selecting and collecting necessary data from among the data sent from the data transmission unit based on collection control information. Therefore, when it is desired to change the collection timing, the necessary data can be easily collected by changing each of the data collection units 3 ₁ to 3 ₃ without changing the data transmission unit 2 . The data collection unit 3 ₁ includes a buffer circuit 4 to which a transfer timing signal CL and data D from a preceding data signal source are applied to an input terminal via the data transmission unit 2; Control information signal P ₁ ,
A collection timing control circuit 5 to which P ₂ and a transfer timing signal CL are applied, and the buffer circuit 4
and a gate circuit 6 connected to the output terminal of the acquisition timing control circuit 5, respectively.

When the data D, the transfer timing signal CL, and the collection control information signals P ₁ and P ₂ are transmitted from the data transmitter 2 to the data collectors 3 ₁ to 3 ₃ , the collection timing of each data collector 3 ₁ is controlled. The circuit 5 updates the control information based on the collection control information, determines the collection timing, opens the gate circuit 6, and collects the necessary data D.

FIG. 3 is a more detailed circuit explanatory diagram of the data collection section, and FIG. 4 is an explanatory diagram of its operation. In the figure, 7 is the acquisition timing control circuit 5.
a NAND circuit, one input end of which is given the collection control information signal _P1 , and the other input end of which is given the collection control information signal _P2 ;
The output terminal of this NAND circuit 7 is connected to a NOR circuit 9 whose one input terminal is supplied with the transfer timing signal CL and whose output terminal is connected to the input terminal of the counter 8.
It is also connected to the clear input terminal of the counter 8 so that the counter 8 can be returned to its initial state (all outputs are zero). 10 is an OR circuit, one input terminal is connected to the output terminal of the NAND circuit 7, and the other input terminal is the output terminal of the comparator 12 connected to the output terminal of the counter 8 and the output terminal of the parameter setting circuit 11. The output terminal of this OR circuit 10 is connected to the gate circuit 6. Although not shown, the counter 8 is configured to have an initial value set when the circuit is powered on. That is, the initial value set by a dip switch or the like is preset by an output pulse from a differential circuit or the like connected to the circuit power supply.

The operation of the data collection section will be further explained. Now, when both the collection control information signals P ₁ and P ₂ are at H level, the output of the NAND circuit 7 is at L level, and the NOR circuit 9 outputs the transfer timing signal.
Apply CL to the input terminal of counter 8. Note that the initial value of the counter 8 at the start of circuit operation is M+1 (M:
1, 2, 3...), the output of the parameter setting circuit 11 is set to M, and the comparator 12 is connected to the counting output N of the counter 8 and the parameter setting circuit 11.
Assuming that an H level signal is output when the magnitude relationship with the output M is N≦M, at this point, the transfer timing signal is sent to the counter 8 via the NOR circuit 9.
Even if CL is given, the count output of counter 8 is M
+1, the output of comparator 12 is L
maintained at the level. Therefore, since the output of the OR circuit 10 is at L level, the gate circuit 6 is in a non-conductive state, and data D is not collected.

Next, when either collection control information signal P ₁ or P ₂ goes to L level, the output signal of NAND circuit 7 goes to H level, and this output signal is given to one input terminal of OR circuit 10, so that the gate Circuit 6 becomes conductive and transfer timing signal
Data D is collected from the output of the buffer circuit 4 latched by CL in accordance with collection timing CL'. In this case, the output signal of the NAND circuit 7 is also given to the clear terminal of the counter 8, the counter 8 is cleared, the count output N of the counter 8 becomes zero, and the output of the comparator 12 becomes H. level.

After that, when the collection control signals P ₁ and P ₂ both go to H level, the output signal of NAND circuit 7 goes to L level, cancels clearing of counter 8, and transfers timing signal CL to counter 8 via NOR circuit 9. becomes a clock and a count input is given. Since the comparator 12 is configured to output an H level output when the count value N of the counter 8 is N≦M, the comparator 12 operates the gate circuit 6 via the OR circuit 10. The data collection is continued, and when the count value N reaches M+1 due to the increment of the counter 8, the output is inverted to L level and the data collection is stopped.

That is, the present invention provides a collection control information signal.
While at least one of P ₁ and P ₂ is at L level, and after both signals P ₁ and P ₂ are changed to H level, comparator 12 is activated according to the set values of counter 8 and parameter 11. Intermediate continuous m
It is configured such that m can be arbitrarily set by changing the initial value of the counter 8 and the set value of the parameter setting circuit 11.

5 and 6 show another embodiment of the present invention, in which one of the collection control information signals P ₁ and P ₂ is at H level,
A multi-stage buffer circuit 41 is provided between the preceding data signal source and the gate circuit 6 so that the previous data can be collected by going back m times based on the time when the other signal changes from the H level to the L _level. ,4
₂ and 4 ₃ are inserted in series. In this case, each buffer circuit 4 ₁ to 4 ₃ is given a transfer timing signal CL.

According to the present invention configured as described above, (a) the acquisition timing can be easily changed by simply changing the acquisition timing control circuit of the data acquisition section.

(b) The data collection section can be easily added to the data transmission section.

(c) By setting the initial value of the counter to M+1 and setting the parameter to M, it is possible to collect data after the reference timing signal minus one set value.

(d) Previous data can be collected retroactively by providing a multi-stage buffer circuit in the data collection section.

It has practical effects such as

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Figs. 2 and 3 are concrete circuit explanatory diagrams, Fig. 4 is an operational explanatory diagram, and Fig. 5 is a diagram illustrating the operation.
The figure shows another embodiment of the present invention, and FIG. 6 is an explanatory diagram of the operation. 1... Data collection control device, 2... Data transmission section,
3 ₁ to 3 ₃ ... data collection section, 4, _{4 1} , 4 ₂ , 4
₃ ... Buffer circuit, 5... Collection timing control circuit, 6... Gate circuit, 7... NAND circuit, 8... Counter, 9... NOR circuit, 10... OR circuit, 11... Parameter setting circuit, 12... Comparator, CL,
CL′...data transfer timing signal, _P1 , _P2 ...collection control information signal, D...data, N...counter count value, M+1...counter initial value, M...parameter setting value.

Claims (1)

[Scope of Claims] 1. A data transmission unit that transmits a collection control information signal instructing collection timing, all data, and a transfer timing signal, and a data collection unit connected to the data transmission unit, The collection section includes a collection timing control circuit that inputs the collection control information signal and the transfer timing signal, determines the collection timing, and outputs it, and a collection timing control circuit that inputs the data and the transfer timing signal and stores the data until the arrival of the next transfer timing signal. It is characterized by comprising a buffer circuit that holds and outputs the buffer circuit, and a gate circuit that passes the output signal of the buffer circuit in accordance with the output signal of the collection timing control circuit, and selectively collects the data based on the collection control information signal. data collection control device. 2. The collection timing control circuit includes a NAND circuit to which a collection control information signal is given to each input terminal, and a NAND circuit to which one input terminal is given a transfer timing signal and the other input terminal is given the output of the NAND circuit. A circuit, a counter whose clock input terminal is connected to the output terminal of the NOR circuit, and whose clear input terminal is connected to the output terminal of the NAND circuit, and the output of the counter and the output of the parameter setting circuit are compared to determine the magnitude. an OR circuit whose one input terminal is connected to the output terminal of the NAND circuit, the other input terminal is connected to the output terminal of the comparator, and whose output terminal is connected to the gate circuit. A data collection control device according to claim 1. 3. The data collection control device according to claim 1, comprising a plurality of stages of buffer circuits.