JPS613457A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the semiconductor circuit device difficult of decrease in insulation strength between the source and drain regions even with a micro transistor gate electrode by a method wherein a transistor gate is formed out of an aperture pattern of photo resist. CONSTITUTION:One main surface of a P type single crystal Si substrate 11 is coated with an Si oxide film 12, and next an N type region 13 of low impurity concentration is formed on the surface of the substrate. Then, a PSG film 14 is grown and is thereafter etched in the part turning into the channel region of the transistor in order to open this film 14. The first photo resist 15 is removed. A P type channel region is formed by ion implantation by using the PSG film 14 as a mask. The patterned film 14 is coated with a polycrystalline Si film and then made to have conductivity by phosphorus diffusion. The second photo resist is formed out of the remaining pattern at the time of forming this transistor gate, and the polycrystalline Si film is patterned by being masked with this resist, resulting in the formation of the transistor gate 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, particularly a short channel MO8).
The present invention relates to a method for manufacturing a run lister.

FIGS. 1(a) to 1(d) show cross-sectional views of the manufacturing process of a conventional MOB transistor.

Conventionally, the manufacturing method of MO8 type transistor is shown in Fig. 1(a).
), a gate insulating oxide film 2 is formed on a silicon substrate 1 having IC conductivity. Next, as shown in Fig. 1 Φ), a polycrystalline silicon film 3 for forming a transistor gate is grown by the CVD method, phosphorus is diffused into this film to make it conductive, and then phosphorography technology is used to make it conductive. , the photoresist 4 is left only in the portion where the gate will be formed. Next, as shown in FIG. 1(e), the above 7
Using the photoresist 4 as a mask, the unnecessary portions of the polycrystalline silicon film 3 are removed by dry etching.
and the transistor gate is created. Using this transristor gate as a mask, impurities having a conductivity type opposite to that of the substrate are diffused near the surface of the substrate using thermal diffusion, ion intrusion, etc., to form source and drain regions 5. A cross-sectional view of the MO8 type transistor manufactured by the above method is shown in FIG. 1(d).

In today's semiconductor integrated circuits, the ability to integrate transistors per chip has improved dramatically compared to previous eras in order to respond to technological development, development, and market demands. In addition, although miniaturization will continue in the future, the conventional technology
7 Using the remaining pattern of the photoresist as a mask, the polycrystalline silicon film was etched to form a transistor gate. For this reason, when the gate length is less than 1 μm,
In order to form the gate electrode of a transistor with a so-called ultra-fine pattern, it is necessary to make the photoresist very thin. In this case, pattern formation becomes extremely difficult and difficult, and the problem arises that the mechanical strength of the resist is insufficient. Furthermore, even if N-type impurity ions are implanted into the substrate using a self-alignment method after forming the transistor gate to form the source and drain regions of the transistor, lateral diffusion of these regions also occurs, lowering the breakdown voltage between the regions. There was a drawback.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor circuit device in which the dielectric strength between the lease and drain regions does not easily drop even with ultra-fine transistor gate electrodes.

Specifically, the method for manufacturing a semiconductor device of the present invention includes, for example, a step of forming a first insulating film on one main surface of a semiconductor substrate having one conductivity type, and a step of forming an impurity having a conductivity type opposite to that of the semiconductor substrate. a step of pressing into a semiconductor substrate, a step of depositing a second insulating film on the first insulating film, a step of patterning the second insulating film into a desired shape, and a step of patterning the second insulating film into a desired shape;
Using the second insulating film as a mask, impurities having the same polarity as the semiconductor substrate are injected to form a channel region, and a polycrystalline silicon film is deposited on the second insulating film, and phosphorus is diffused into this to make it conductive. A process of patterning this polycrystalline silicon film into a desired shape to form a transistor gate, and a process of forming a drain of a transistor using this patterned polycrystalline silicon film as a mask. It is characterized by

According to the present invention, since the transistor gate is formed with a pattern of openings in the photoresist, the gate pattern can be formed with finer dimensions than the remaining photoresist pattern, and the impurity density in the source and drain regions can be reduced. Lightly Do
Since a ped drain structure can be realized, there is an advantage that the source-drain breakdown voltage does not easily drop even if the transistor gate length is shortened.

Next, embodiments of the present invention will be described using the drawings.

First, as shown in FIG. 2(a), a silicon oxide film 12, which is a first insulating film, is deposited on one main surface of a P-type nested crystalline silicon substrate 11 by thermal oxidation. Next, a uniform N-type region 13 with a low impurity concentration is formed on the substrate surface by thermal diffusion or ion implantation through this oxide film.

Next, as shown in FIG. 2, a phosphorus silicon glass (PSG) film 14, which is a second insulating film, is grown. After that, the portion that will become the channel region of the transistor is
To open holes in the Sc+ film 14, a first photoresist is applied and the PEG film 14 is etched using lithographic techniques. At this time, if the wet etch method is used, the PSG film has not been subjected to heat treatment yet, so
There is a difference in etching rate between the silicon oxide film 12 and the PSG film 13, and only the PSG film can be removed. After this, the 7th photoresist 15 of the cylinder 1 is removed.

Next, as shown in FIG. 2C, a P-type channel region is formed by ion implantation using the PSG film 14 as a mask. At this time, since the N-type impurity region 13 is formed in the channel region before the ion implantation process,
This process must diffuse enough impurities to change the N-type conductivity to P-type groove conductivity. Further, the first 7-hole resist 15 may be removed after this process. Also, the first
Even if the oxide film 12 is removed after these treatments and a new oxide film is deposited by thermal oxidation, no problem will occur.

Next, as shown in FIG. 2(d), a polycrystalline silicon film is deposited on the patterned P8G film 14 by the CVD method, and phosphorus is diffused into the film to make it conductive.

When forming this transistor gate, a second photoresist is left in the pattern with a width that does not cause problems with the mechanical strength of the photoresist, and a margin of the N-region of the LDD structure. Using this as a mask, the polycrystalline silicon film is patterned by dry etching to form a transistor gate 16.

Next, as shown in FIG. 2(e), N-type impurity source and drain regions 17 are formed by ion implantation using the transistor gate 16 as a mask. The N-type impurity concentration at this time is used for the current transistor formation. The concentration is usually expressed as N+, and the concentration is higher than that of the N-type phosphorus 13 shown in FIG. 2(a).

Next, as shown in FIG. 2(f), the polycrystalline silicon film that is the transistor gate 16 is etched back to remove the portion extending from the channel region to the source and drain regions. The sliding reduces the stray capacitance between the gate and the diffusion layer, improving the switching of the transistor and making the device planar.

As described above, by using the manufacturing method and structure according to the present invention, it is possible to form ultra-fine transistor gates with existing technology, and also to realize an LDD structure. It is possible to realize a transistor, and its effects are significant.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing an MO8 type transistor according to the prior art, and FIG.
5. Explanation of symbols 1, 11...Silicon substrate, 2.12...
...Thermal oxide film, 4.15...Photoresist, 3,16...Polycrystalline silicon film (Ga)),
5.13.17...N-type impurity diffusion layer, 14.
Old...PSG film. ((1) 1 ↓ +++ (C) −(θu<b) CC) Figure 2 JJJ JJJ (Nano Figure 2

Claims (1)

[Claims] An impurity region of an opposite conductivity type is formed on one main surface of a semiconductor substrate having one conductivity type, and an impurity region of a different material from that on the first insulating film is formed on a first insulating film provided on the one main surface. A predetermined portion of the second insulating film is removed, and an impurity having the same conductivity type as that of the semiconductor substrate is applied to the semiconductor substrate using the remaining second insulating film as a mask. By introducing a part of the impurity region of the opposite conductivity type into one conductivity type, it is used as a channel region, and then a gate electrode is partially formed from above the channel region onto the second insulating film around it. 1. A method of manufacturing a semiconductor device, comprising: forming a deep junction between source and drain regions by introducing impurities of opposite conductivity type into a semiconductor substrate using the gate electrode as a mask.