JPS6134256B2 - - Google Patents
Info
- Publication number
- JPS6134256B2 JPS6134256B2 JP55132014A JP13201480A JPS6134256B2 JP S6134256 B2 JPS6134256 B2 JP S6134256B2 JP 55132014 A JP55132014 A JP 55132014A JP 13201480 A JP13201480 A JP 13201480A JP S6134256 B2 JPS6134256 B2 JP S6134256B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thickness
- metal wiring
- resin
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 230000008646 thermal stress Effects 0.000 description 9
- 230000008602 contraction Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Description
【発明の詳細な説明】
本発明は半導体装置にかかり、とくに樹脂封止
半導体基板表面部分の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a surface portion of a resin-sealed semiconductor substrate.
樹脂封止半導体装置の配線部分の断面は通常第
１図に示すごとく、一導電形の半導体基板１の主
たる表面に酸化絶縁膜（以下では第１酸化膜と記
す）２が形成され、その上部の必要箇所に該半導
体装置内配線用の金属配線３が形成され、しかる
後に該半導体装置の主表面に水分や不純物が侵入
することを防止する目的で酸化絶縁膜（以下では
カバー酸化膜と記す）４が形成されており、最終
的には該半導体装置は樹脂５で封止されている。 As shown in FIG. 1, the cross section of the wiring portion of a resin-sealed semiconductor device is usually such that an oxide insulating film (hereinafter referred to as a first oxide film) 2 is formed on the main surface of a semiconductor substrate 1 of one conductivity type, and the upper Metal wiring 3 for internal wiring of the semiconductor device is formed at necessary locations, and then an oxide insulating film (hereinafter referred to as a cover oxide film) is formed for the purpose of preventing moisture and impurities from entering the main surface of the semiconductor device. ) 4 is formed, and the semiconductor device is finally sealed with resin 5.
前記構造を有する半導体装置において従来は第
１図に示すごとく、金属配線３の厚みH1とカバ
ー酸化膜４の厚みH2とは次のような関係にあつ
た。 Conventionally, in a semiconductor device having the above structure, as shown in FIG. 1, the thickness H 1 of the metal wiring 3 and the thickness H 2 of the cover oxide film 4 have had the following relationship.
H1＞H2 ……(1)
一般的には金属配線３の厚みH1はカバー酸化
膜４の厚みH2の２倍程度であつた。 H 1 >H 2 (1) Generally, the thickness H 1 of the metal wiring 3 is about twice the thickness H 2 of the cover oxide film 4.
しかるに、上記(1)式が成立する構造を有する従
来の樹脂封止半導体装置を低温と高温の雰囲気に
くり返しさらした場合、すなわち低温と高温の熱
ストレスが、従来の樹脂封止半導体装置にくり返
し印加された場合には、樹脂の硬化収縮及び樹脂
と半導体装置との熱膨張係数の相違により、第３
図に示すごとく樹脂５の収縮による機械的圧力Ｆ
が金属配線３に半導体基板１とほぼ平行に印加さ
れ、金属配線３は正常な形状を保ち得ず半導体基
板１と平行方向に移動を開始する。同時にカバー
酸化膜４には亀裂が生じる。最終的には金属配線
３にも亀裂が発生し、金属配線３は断線状態とな
る。すなわち半導体装置は破壊に至らしめられ
る。 However, when a conventional resin-sealed semiconductor device having a structure in which formula (1) holds true is repeatedly exposed to low and high temperature atmospheres, that is, thermal stress at low and high temperatures is repeatedly applied to the conventional resin-sealed semiconductor device. If the voltage is
As shown in the figure, mechanical pressure F due to contraction of resin 5
is applied to the metal wiring 3 substantially parallel to the semiconductor substrate 1, and the metal wiring 3 cannot maintain its normal shape and starts moving in a direction parallel to the semiconductor substrate 1. At the same time, cracks occur in the cover oxide film 4. Eventually, cracks occur in the metal wiring 3 as well, and the metal wiring 3 becomes disconnected. In other words, the semiconductor device is destroyed.
通常前記熱ストレスが樹脂封止半導体装置にく
り返し印加された場合には該樹脂は膨張・収縮を
くり返すが、樹脂はしだいに硬化するので樹脂の
硬化収縮により、該半導体装置には周辺部から中
心点へ向けて半導体基板１とほぼ平行に印加され
る機械的圧力Ｆが最も強力に作用する。従つて金
属配線３は通常半導体装置の中心方向へ移動す
る。また半導体装置の高集積化に伴ない、半導体
装置が大型化してきたので前記熱ストレスのくり
返し印加による金属配線３の断線現象は樹脂封止
半導体装置の代表的故障現象のひとつになつてき
た。 Normally, when the above-mentioned thermal stress is repeatedly applied to a resin-sealed semiconductor device, the resin expands and contracts repeatedly, but since the resin gradually hardens, the resin seals and shrinks, causing the semiconductor device to be damaged from the periphery. The mechanical pressure F applied toward the center point substantially parallel to the semiconductor substrate 1 acts most strongly. Therefore, the metal wiring 3 normally moves toward the center of the semiconductor device. Further, as semiconductor devices have become larger with the increase in the degree of integration of semiconductor devices, the phenomenon of disconnection of the metal wiring 3 due to the repeated application of thermal stress has become one of the typical failure phenomena of resin-sealed semiconductor devices.
本発明の目的は、このような従来の樹脂封止半
導体装置の欠点を解消し、熱的ストレスがくり返
し印加されても破壊されない樹脂封止半導体装置
を提供することにある。 An object of the present invention is to eliminate such drawbacks of conventional resin-sealed semiconductor devices and to provide a resin-sealed semiconductor device that will not be destroyed even if thermal stress is repeatedly applied.
本発明による樹脂封止半導体装置は、配線部分
の断面図を第２図に示すごとく、該半導体装置内
配線用の金属配線３の厚みH1はカバー酸化膜４
の厚みH2より小である構造を有することを特徴
とする。すなわち
H1＜H2 ……(2)
とする。 In the resin-sealed semiconductor device according to the present invention, as shown in FIG. 2, a cross-sectional view of the wiring portion, the thickness H 1 of the metal wiring 3 for wiring inside the semiconductor device is equal to the cover oxide film 4.
It is characterized by having a structure having a thickness smaller than H2 . In other words, H 1 <H 2 ...(2).
次に本発明の特徴を実施例を用いて説明する。
第４図は本発明による樹脂封止半導体装置に熱ス
トレスがくり返し印加された場合の配線部分の断
面図である。実施例では金属配線３の厚みH1を
1.2μｍ（ミクロン）、カバー酸化膜４の厚みH2を
1.6μｍ（ミクロン）とする。すなわち金属配線
３の厚みH1とカバー酸化膜４の厚みH2との関係
はは前記(2)式を満足するものとする。同図におい
て熱ストレスのくり返し印加による機械的圧力Ｆ
がカバー酸化膜４に対して半導体基板１とほぼ平
行に印加された場合、前述のごとく金属配線３の
厚みH1はカバー酸化膜４の厚みH2より0.4μｍ
（ミクロン）小であるが由に、前記機械的圧力Ｆ
は金属配線３に対しては影響を及ぼさない。 Next, features of the present invention will be explained using examples.
FIG. 4 is a cross-sectional view of the wiring portion when thermal stress is repeatedly applied to the resin-sealed semiconductor device according to the present invention. In the example, the thickness H 1 of the metal wiring 3 is
1.2 μm (micron), thickness H 2 of cover oxide film 4
1.6μm (micron). That is, the relationship between the thickness H 1 of the metal wiring 3 and the thickness H 2 of the cover oxide film 4 satisfies the above equation (2). In the same figure, mechanical pressure F due to repeated application of thermal stress
is applied to the cover oxide film 4 almost parallel to the semiconductor substrate 1, the thickness H 1 of the metal wiring 3 is 0.4 μm smaller than the thickness H 2 of the cover oxide film 4 as described above.
Although the mechanical pressure F is small (microns),
does not affect the metal wiring 3.
さらにカバー酸化膜４の厚みH2も従来の数倍
となる為、カバー酸化膜４の機械的強度も向上し
ている。 Furthermore, since the thickness H 2 of the cover oxide film 4 is several times that of the conventional one, the mechanical strength of the cover oxide film 4 is also improved.
すなわち本発明によれば、熱ストレスがくり返
し印加された場合においても、金属配線４の移動
による破壊現象が生じることのない樹脂封止半導
体装置が提供される。 That is, according to the present invention, there is provided a resin-sealed semiconductor device that does not suffer from destruction due to movement of the metal wiring 4 even when thermal stress is repeatedly applied.
実施例においてはカバー酸化膜４は一種類とし
てあるが、異なる性質あるいは異なる材質のカバ
ー酸化膜を多層で形成した場合においても、各々
のカバー酸化膜の厚みを合計した最終的なカバー
酸化膜全体の厚みH2が前記(2)式を満足すれば前
記実施例と同様の効果が得られる。 In the embodiment, one type of cover oxide film 4 is used, but even when multiple layers of cover oxide films with different properties or materials are formed, the total thickness of the final cover oxide film is the sum of the thicknesses of each cover oxide film. If the thickness H 2 satisfies the above formula (2), the same effect as in the above embodiment can be obtained.
第１図は従来の樹脂封止半導体装置の配線部分
の断面図、第２図は本発明の実施例による樹脂封
止半導体装置の配線部分の断面図、第３図は従来
の樹脂封止半導体装置に熱ストレスがくり返し印
加された場合の配線部分の断面図、第４図本発明
の実施例に熱ストレスがくり返し印加された場合
の配線部分の断面図である。
尚、図において、１……半導体基板、２……第
１酸化膜、３……金属配線、４……カバー酸化
膜、５……樹脂、H1……金属配線の厚み、H2…
…カバー酸化膜の厚み、Ｆ……機械的圧力、であ
る。
FIG. 1 is a cross-sectional view of a wiring portion of a conventional resin-sealed semiconductor device, FIG. 2 is a cross-sectional view of a wiring portion of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a wiring portion of a conventional resin-sealed semiconductor device. FIG. 4 is a cross-sectional view of the wiring portion when thermal stress is repeatedly applied to the device; FIG. 4 is a cross-sectional view of the wiring portion when thermal stress is repeatedly applied to the embodiment of the present invention. In the figure, 1...semiconductor substrate, 2...first oxide film, 3...metal wiring, 4...cover oxide film, 5...resin, H1 ...thickness of metal wiring, H2 ...
... Thickness of cover oxide film, F ... Mechanical pressure.
Claims (1)
配線、金属配線等を形成し、前記信号経路用半導
体配線、金属配線等を含む表面に酸化絶縁膜を介
して樹脂封止した半導体装置において、前記酸化
絶縁膜の厚みは少なくとも前記金属配線の厚みよ
り大であることを特徴とする半導体装置。1. A semiconductor device in which semiconductor wiring for signal paths, metal wiring, etc. are formed on the main surface of a semiconductor substrate, and the surface including the semiconductor wiring for signal paths, metal wiring, etc. is sealed with resin via an oxide insulating film, A semiconductor device characterized in that the thickness of the oxide insulating film is at least greater than the thickness of the metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13201480A JPS5756949A (en) | 1980-09-22 | 1980-09-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13201480A JPS5756949A (en) | 1980-09-22 | 1980-09-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5756949A JPS5756949A (en) | 1982-04-05 |
| JPS6134256B2 true JPS6134256B2 (en) | 1986-08-06 |
Family
ID=15071510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13201480A Granted JPS5756949A (en) | 1980-09-22 | 1980-09-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5756949A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5161781A (en) * | 1974-11-27 | 1976-05-28 | Hitachi Ltd | TAISHITSUSEIOKOJOSHITAHANDOTAISOCHI |
| JPS5422775A (en) * | 1977-07-22 | 1979-02-20 | Hitachi Ltd | Semiconductor device |
| JPS5555538A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor device |
-
1980
- 1980-09-22 JP JP13201480A patent/JPS5756949A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5161781A (en) * | 1974-11-27 | 1976-05-28 | Hitachi Ltd | TAISHITSUSEIOKOJOSHITAHANDOTAISOCHI |
| JPS5422775A (en) * | 1977-07-22 | 1979-02-20 | Hitachi Ltd | Semiconductor device |
| JPS5555538A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5756949A (en) | 1982-04-05 |
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