JPS613397A - Josephine memory device having semi-symmetric cell structure - Google Patents

Abstract

PURPOSE:To attain the high integration, high speed operation and drive system for grounding a distance end, to shorten an operating time and to enlarge a dynamic range by disposing memory cells except the 1st word selection line parts so as to be symmetrical each other, and arranging the 1st word selection lines every other cell in the folded-back state. CONSTITUTION:A memory cell matrix is constituted in such a way that four cells are basically disposed as one unit vertically and horizontally with repetition. Write gates 111-114, read gates 121-124, memory loops 131-134, D line, S line and a Y line of a word selection line are disposed symmetrically with respect to X and Y axes. However, the distant end of the Y line is grounded, and its current flows in the same direction in the entire memory matrix. The X line of the word selection line is disposed every other cell by folding back. All currents of the X line flow in the same direction. As a result, currents of the X and Y lines are added in the same direction, and a write gate of words at the intersection of the memory matrix where bth currents flow is selectively switched. Accordingly, information of the D line is written. Currents flow in the S and D lines so that their current directions can be equal. Thus a drive current rises quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention provides a storage device using a digital device.
In particular, it relates to the structure of a memory cell matrix for storing information.

(Prior art and its problems) Until now, as a memory circuit using a Josephson device, there has been proposed a storage circuit using a Josephson device, as disclosed in Japanese Patent Publication No. 51-113544 (Reference Document 1).
A circuit for destructively reading out stored information as described in 1986-120341 (Reference Document 2) and a circuit for reading out stored information in a destructive manner as described in Japanese Patent Application Publication No. 1987-120341 (Reference Document 2) and 1987-73530 (Reference Document 3) A circuit that non-destructively reads out the data (hereinafter referred to as NDRO method) is known. Typically, these memory devices are constructed by arranging all the basic memory cells in a matrix. This memory cell? The layout is logically the same circuit with the same shape at the bottom of the groove.

However, in actual devices, it is difficult to repeatedly arrange cells of the same shape due to structural limitations of the lower electrode, junction, upper electrode, and control line for switching all the devices. . For this reason, conventionally,
I.E.I.E. Journal Op Solid
State Circuit Vol. 5C-14 No. 5 No. 794 (Reference document 1: IEEE Journal of 5
olid-8tate C1rcuits.

Vol, 5C-14#j, 5. PP, 7?4-
796, Oct.

Henkel et al. (W, H. 1979).

The IJ wax composition invented by John Henkel, in which memory cells were arranged symmetrically, was used.

FIG. 1 shows the basic structure of four cells constituting this memory cell matrix. The four memory cells are write gates 11 to 14 using a quantum interferometer composed of a Josephson device and an inductance, and read gates 21 to 14 using a quantum interferometer also composed of a Josephson device and an inductance. 24 and memory loop 3
It consists of numbers 1 to 34. Each memory cell is arranged symmetrically with respect to the X and Y axes as shown in the figure. A conventional NDRO type Josephson memory device is constructed by repeatedly arranging the four cells shown in FIG. 1 in the same shape. Therefore, the configuration C of this memory cell matrix is based on the X-rays (X
, -X, lX, -X2), Y line (Yr-YI
, Yz-Y2), and the D line (D
I-DI+D2-D2) and S line (S+-8+-82) as a sense line for reading written information.
-82), it was necessary to match the direction of the current signal, so it was always required to be installed on D#jl'. For this reason, the rise and fall portions of the TL multiplier signal applied to each line are delayed by the time during which the signal is transmitted, thereby slowing down the operation time of the storage device. Furthermore, since an area is required for arranging all the return lines, the M structure of the storage device is complicated, and the miniaturization and high integration of the device are restricted.

Note that in FIG. 1, the return lines for each line are not shown to make the diagram easier to read, but in reality, the return lines for each line are arranged respectively. Further, in conventional storage devices, it is not possible to adopt a circuit system in which the ρ line is removed, the far end is grounded, and the near end is driven. In other words, if you exclude the back line, the direction of current flowing through each line is different for each Vk contact cell, so it becomes necessary to alternately arrange positive and negative drive circuits as drive circuits, which makes the circuit configuration extremely complicated. It was difficult. Furthermore, conventionally, a magnetically coupled circuit as described in Document 4 has been used as a drive circuit for driving each word selection line. Since the drive circuits of this system are connected to each other, crosstalk occurs between adjacent word selection lines due to switches in the drive circuits, narrowing the operating area of the write gate.

(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide a Josephson memory device having a semi-symmetrical cell structure that is highly integrated and operates at high speed. Still another object is to enable a drive system in which the far end is entirely grounded, thereby further shortening the operating time and expanding the operating range.

(Structure of the Invention) According to the present invention, at least a first word selection line and a second word selection line that perform all word selection, and a column line that provides written information during writing and performs word selection during reading. , a storage means for holding information, a sense line for reading written information, a writing means for writing information into the storage means, and a reading device for outputting stored information of a selected word position to the sense line. In a Josephson memory device configured by arranging a plurality of memory cells including a first word selection line portion, the memory cells with weights removed from the first word selection line portion are arranged symmetrically to each other; A Josephson memory device having a semi-symmetrical cell structure is obtained in which the word selection line of 1 is folded back every other cell.

(Detailed Description of Configuration) The present invention solves all the problems of the prior art by adopting the above-mentioned configuration. FIG. 2 shows a four-cell configuration with a semi-symmetrical cell structure as a preferred embodiment of the present invention. The memory cell matrix of the memory device according to the present invention is constructed based on the four cells shown in FIG. 2, which are arranged repeatedly in the vertical and horizontal directions in the same shape. Write gate 111-1
14. Read sigate 121-124. memory loop 131
~134°The D line, which serves as a digit line that provides write data during writing and selects words during reading, and the sm line, which serves as a sense line that reads information in the memory loop, are connected to the X axis as in the conventional example shown in FIG. and are arranged symmetrically about the Y axis. The Y line, which is the second word selection line that performs word selection during writing, is arranged symmetrically with respect to the X and Y axes as in the conventional example, but the Y line is removed and placed on the opposite side of the drive circuit, that is, far away. The end is grounded. The current in the Y line is caused to flow in the same direction, for example from top to bottom in FIG. 2, in all of the memory matrices, unlike the conventional one. , the X-ray, which is the first word selection line that covers all word selection rows during writing, is arranged in a folded manner every other cell. In FIG. 2, write gates 112, 113
The X-rays that control all the switches are folded back. In the present invention, the source bi of the X-rays is removed, and the far end of the X-rays is grounded, similar to the Y-rays. The X-rays flow in the same direction, for example from left to right in FIG. 2. Therefore,
The currents of the x7 and Y lines that control the switches 111 to 114 are added in the same direction, and the write gate of the word at the intersection of the memory matrix where the X-ray and Y-line currents flow together is selectively switched. Then, the information on the D line is written. At this time, the relationship between the current direction of the D line and the current direction of the Since it has no direction, it is not a problem. That is, X
, have the same threshold for positive and negative currents in the Y line.

On the other hand, regarding the relationship between the S line in the read gates 121 to 124 and the circulating current in the storage loops 131 to 134,
Since the threshold conductivity of the read gate changes depending on the direction of the circulating current, the circulating current is matched with the current direction of the S line. That is, in each reading signal, Sa
Current is passed through the S line and the D line so that the relationship between the current directions of the S line and the D line is the same as shown in FIG. Although the D line and the S line overlap the return line, the return line is omitted in FIG. 2 to make the drawing easier to read.

(Embodiment) FIG. 3 is a block diagram schematically showing the configuration of a storage device embodying the present invention. Semi-symmetric cell structure according to the invention? The Josephnon memory device has a memory matrix 291 constructed by repeatedly arranging all the semi-symmetric basic four cells shown in FIG. YD decoder 2 generated
03, the drive circuit 204 for the Y line and D#Ii, the remaining part 205 of the address signal, and the selection of the Xm and S lines (7f
XS decoder 206 that generates f, X-rays and S droplets! An XS drive circuit 207 that supports all reading) and a sense circuit 20 that combines all reading) signals and sends an output signal to a terminal 211.
It consists of 8. Write data is input from the terminal 212 and all data is sent to the D line drive circuit 204.

A signal designating reading or writing is input from the terminal 213 and controls the drive circuit for each line. Note that in this embodiment, the control lines for controlling the entire storage device are not shown, but they must be
7 gives an additional formula.

Further, as a feature of the present invention, the X-ray and Y-ray drive circuits Th, b4. zo
s is a resistor combination circuit or the like which operates independently. Therefore, since the word lines are separated from each other, loss talk, which occurs in conventionally used magnetically coupled drive circuits, is eliminated and the entire operating area of the write gate is expanded.

(Effects of the Invention) As described above, the Sefson memory device having a semi-symmetrical cell structure according to the present invention has a basic four-cell structure constituting a memory cell matrix, in which the first word selection plate is folded back for each cell. It is characterized by having an asymmetric structure arranged, a structure arranged symmetrically except for the first word selection line, and a structure except the first word line.

Therefore, in addition to the above-mentioned embodiment, one in which a plurality of memory matrices having such a structure are arranged on one chip can be considered as another embodiment. X-ray which is each word selection line,
By removing the return line of the Y line, it is possible to eliminate the drive method of grounding the far end, speeding up the rise of the drive current and reducing crosstalk between word selection lines, resulting in high-speed memory. A device is obtained. Furthermore, even if there is no BS, each word selection line can be driven by a drive circuit with the same polarity, which simplifies the drive circuit.
The device can be made smaller.

As described above, by implementing the present invention, a fast and compact storage device can be obtained.

, ;:$1 Figure shows the conventional description 1. Figure 2 shows the basic structure of the four cells that make up the symmetric storage cell matrix of the device; FIG. 3 shows the structure of a storage device embodying the invention.

11-14, 111-114・Write gate, 21-2
4.121~124 ・Reading loss gate, 31~34.
) 131-134...Memory loop, 201...Indication 1 cell address, $202...Address signal, 2
03-... YD decoder, 204... YD le 1 operation circuit,
206... XS decoder, 207... XS drive circuit, 208 - Sense circuit, 211... Read (i output terminal, 2] 2... Data signal input terminal, 213...
・Read/write designation signal input terminal.

Patent applicant: mr Tanishima shield Y axis for 1, v; 4, n

Claims (1)

[Claims] At least a first word selection line and a second word selection line for selecting a word, a column line for giving written information at the time of writing and performing word selection at the time of reading, a storage means for retaining the information, and a memory means for retaining the information. Consisting of a plurality of memory cells each including a sense line for reading information, a writing means for writing information into the memory means, and a reading means for outputting memory information of a selected word position to the sense line. The Josephson memory device is characterized in that the memory cells except for the first word selection line portion are arranged symmetrically, and the first word selection line is folded back every other cell. A Josephson memory device with a semisymmetric cell structure.