JPS6133216B2 - - Google Patents

Info

Publication number
JPS6133216B2
JPS6133216B2 JP53138691A JP13869178A JPS6133216B2 JP S6133216 B2 JPS6133216 B2 JP S6133216B2 JP 53138691 A JP53138691 A JP 53138691A JP 13869178 A JP13869178 A JP 13869178A JP S6133216 B2 JPS6133216 B2 JP S6133216B2
Authority
JP
Japan
Prior art keywords
circuit
logic
parity
data
comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53138691A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5566031A (en
Inventor
Noritaka Umeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13869178A priority Critical patent/JPS5566031A/ja
Publication of JPS5566031A publication Critical patent/JPS5566031A/ja
Publication of JPS6133216B2 publication Critical patent/JPS6133216B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP13869178A 1978-11-10 1978-11-10 Data comparator circuit Granted JPS5566031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13869178A JPS5566031A (en) 1978-11-10 1978-11-10 Data comparator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13869178A JPS5566031A (en) 1978-11-10 1978-11-10 Data comparator circuit

Publications (2)

Publication Number Publication Date
JPS5566031A JPS5566031A (en) 1980-05-19
JPS6133216B2 true JPS6133216B2 (show.php) 1986-08-01

Family

ID=15227853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13869178A Granted JPS5566031A (en) 1978-11-10 1978-11-10 Data comparator circuit

Country Status (1)

Country Link
JP (1) JPS5566031A (show.php)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757504A (en) * 1986-04-21 1988-07-12 Texas Instruments Incorporated Polyphase parity generator circuit

Also Published As

Publication number Publication date
JPS5566031A (en) 1980-05-19

Similar Documents

Publication Publication Date Title
US4707800A (en) Adder/substractor for variable length numbers
US5508950A (en) Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum
US3993891A (en) High speed parallel digital adder employing conditional and look-ahead approaches
US4953115A (en) Absolute value calculating circuit having a single adder
US3100835A (en) Selecting adder
Langdon et al. Concurrent error detection for group look-ahead binary adders
US5331645A (en) Expandable digital error detection and correction device
US3925647A (en) Parity predicting and checking logic for carry look-ahead binary adder
US20030140080A1 (en) Wide adder with critical path of three gates
JPS595349A (ja) 加算器
US3649817A (en) Arithmetic and logical unit with error checking
US6584485B1 (en) 4 to 2 adder
EP0068109B1 (en) Arithmetic and logic unit processor chips
US4224680A (en) Parity prediction circuit for adder/counter
Kumar et al. On-line detection of faults in carry-select adders
GB1579100A (en) Digital arithmetic method and means
US5539332A (en) Adder circuits and magnitude comparator
US5506800A (en) Self-checking complementary adder unit
US3758760A (en) Error detection for arithmetic and logical unit modules
US6088763A (en) Method and apparatus for translating an effective address to a real address within a cache memory
JPS6133216B2 (show.php)
Vasudevan et al. A technique for modular design of self-checking carry-select adder
JPH06195201A (ja) 不等桁上げ方式(varied carry scheme)を用いた高速加算器とそれに関連する方法
US5515506A (en) Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle
US4924423A (en) High speed parity prediction for binary adders using irregular grouping scheme