JPS6132569A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase storage capacitance, to reduce the quantity of dry etching for forming a groove and to minimize damage to a substrate by forming a side- wall opening section in width wider than a surface opening section and using the inner wall of the side-wall opening section as an electrode surface. CONSTITUTION:An silicon oxide film 32 is patterned to the surface of an silicon substrate 31, and the silicon substrate 31 is dry-etched vertically while using the silicon oxide film 32 as a mask to shape an opening section 33. An silicon oxide film 34 is formed. The silicon oxide film 34 is etched in an anisotropic manner to leave the silicon oxide film 34 only on the side surface of the opening section 33. The silicon substrate 31 is etched in an isotropic manner from the base of the opening section 33 to shape a second opening section 35. The silicon oxide films 32 and 34 are removed, and a dielectric film 36 represented by a film such as the silicon oxide film is formed onto the surface of the silicon substrate and the surface of the opening section. A polycrystalline silicon film 37 is buried into the opening section.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a fine trench capacitor with a large storage capacity, and particularly to the structure of the storage capacitance of a large capacity MOS dynamometer memory cell.

Conventional configurations and their problems In recent years, large capacity MOS dynamic RAM (Random
There has been remarkable progress in increasing the degree of integration of Access Memory (Access Memory). The technology supporting this is miniaturization of memory cells.

A memory cell of a MOS dynamic RAM is composed of a switching transistor and a storage capacitor, and FIG. 1 shows a cross-sectional view of the structure of a conventional memory cell.

1 is a P-type silicon substrate, 2 is a field oxide film, 3 is a capacitor dielectric film made of, for example, a silicon oxide film, 4 is a gate electrode represented by polycrystalline silicon, and 6 is a high concentration N
The type source/drain diffusion region 6 is a plate electrode made of polycrystalline silicon, for example. Q constitutes a switching transistor, and C8 constitutes a storage capacitor.

In the above memory cell, the storage capacitor is formed by a MOS capacitor whose dielectric film is a silicon oxide film formed on the surface of the substrate. However, as the area of the capacitor becomes smaller, the amount of accumulated charge decreases.

The maximum accumulated charge amount Qms of the capacitor is as follows, where εi+Ti is the dielectric constant and film thickness of the dielectric film, S is the area of the capacitor, and Vs is the signal voltage.

In order to improve Qms, it is sufficient to increase εl + S+ v8 or decrease Ti.

In order to increase εi, it is necessary to use a dielectric film having a higher dielectric constant than the currently widely used silicon oxide film. For example, the T turtle 205 is 6 to 1 times larger than the silicon oxide film.
Although it has an εi that is 0 times larger, it has drawbacks such as recrystallization at high temperatures of 900° C. or higher, which increases leakage current. Furthermore, increasing the signal voltage VS or decreasing the film thickness Ti of the dielectric film has problems such as lowering the breakdown voltage of the dielectric film and reducing reliability.

In Figure 2, using the conventional proven value of εl + ``l * vI!!, and increasing the area S of the capacitor, Q
FIG. 3 is a structural cross-sectional view of a memory cell with increased ms. 11
12 is a P-type silicon substrate, 12 is a field oxide film, 13 is a capacitor dielectric film, 14 is a gate electrode, 15 is a source and drain region, and 16 is a plate electrode. In FIG. 2, a vertical groove is dug in the silicon substrate, and the inner wall of the groove is used as the electrode surface of the capacitor, thereby increasing the charge storage area.

Thereby, sufficient storage capacity can be ensured even if the cell area is reduced. However, a directional dry etching method is required to process the grooves, and there is a limit to the depth of the grooves, and damage remains due to deep dry etching, resulting in reliability problems.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems and aims to provide a fine trench capacitor with a large storage capacity.

Structure of the Invention The present invention is a trench type capacitor having an inner wall area larger than the surface opening area, and can have a sufficiently large storage capacity even when miniaturized.

DESCRIPTION OF EMBODIMENTS [Embodiment 1] FIG. 3 shows a structural cross-sectional view of a trench type capacitor in one embodiment. In FIG. 3, 21 is a silicon substrate, 22 is a capacitor dielectric film represented by, for example, a silicon oxide film, and 23 is a plate electrode made of, for example, a polycrystalline silicon film.

-The MOS capacitor is constructed by using a silicon oxide film 22 formed on the inner wall surface of a vertical groove formed from the surface of a substrate 21 as a dielectric film, and using the substrate 21 and a polycrystalline silicon film 23 as electrodes, respectively. The groove has a shape in which the width of the side wall opening below the groove is wider than the width of the surface opening, and the inner wall area is larger than that of a conventional vertical groove when the groove depth is the same and the surface opening area is the same. Therefore, the storage capacity is also large. Also width a
Depth hf of the opening: As long as the depth hf is at least the depth that will become the active region of the device formed on the surface of the silicon substrate, the opening area of the width will not affect the device formation, and therefore it will be easier to miniaturize the device. There is no problem.

[Embodiment 2] FIGS. 4(IL) to 4(f') are process cross-sectional views illustrating a method of forming a trench type capacitor in an embodiment of the present invention.

In FIG. 4 (IL), a silicon oxide film 32 is patterned on the surface of a silicon substrate 31.
Using the mask as a mask, the silicon substrate 31 is vertically dry-etched to form an opening 33. Next, as shown in FIG. 4, a silicon oxide film 34 is formed. Next, Figure 4 (C)
As shown in FIG. 3, the silicon oxide film 34 is anisotropically etched, leaving the silicon oxide film 34 only on the side surfaces of the opening 33.

Next, as shown in FIG. 4 (+1), the silicon substrate 31 is isotropically etched from the bottom surface of the opening 33 to form a second opening 36. Next, as shown in FIG. 4(e), after removing the silicon oxide films 32 and 34, a dielectric film 36, typified by a silicon oxide film, is formed on the surface of the silicon substrate and the surface of the opening. Next, a polycrystalline silicon film 37 is buried inside the opening as shown in FIG. 4(f').

As described above, according to this embodiment, the inner wall area of the groove can be increased by making the inner width of the groove wider than in a groove type capacitor made of vertical grooves having the same opening width and the same depth. Therefore, the storage capacity is also large. Further, the amount of dry etching needed to form a groove of a predetermined depth is less than that required for forming a conventional vertical groove, thereby reducing damage to the substrate.

[Example 3] FIG. 5 is a process sectional view showing another embodiment of the present invention.

In FIG. 6(a), a silicon substrate 41 has a high concentration of n.
After forming the buried region 42, an epitaxial layer 43 is grown. Next, as shown in FIG. 6(b), the resist 44
Using the mask as a mask, the epitaxial layer 43 is vertically dry etched to form an opening 46. Next, as shown in FIG. 6(0), after removing the resist 44, the n-buried region 42 is selectively etched to form an opening 46. When a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used as the etching solution, etching proceeds several tens of times faster in the high concentration n region than in the low concentration region, and the openings 46 can be selectively formed. Next, Figure 6 (+
As shown in 1), a dielectric film 47 typified by, for example, a silicon oxide film is formed on the inner walls of the openings 46 and 46, and polycrystalline silicon 48 is buried inside the openings.

As described above, according to this embodiment, the width of the lateral grooves continuous below the vertical grooves is determined by the width of the n+ buried region formed in advance, and it is possible to form lateral grooves with a sufficiently wide width in a well-controlled manner. is possible. Further, the relative positional relationship between the vertical grooves and the horizontal grooves is arbitrary and can be freely selected according to the mask. Furthermore, at this time, the total area inside the groove remains unchanged, and therefore the value of the storage capacitance remains unchanged.

Work example 4] FIG. 6 is a process sectional view showing another embodiment of the present invention.

In FIG. 6(&), a silicon substrate 41 has a high concentration of n.
After forming the buried region 42, an epitaxial layer 43 is grown, followed by forming an n+ buried region 44 in the epitaxial layer 43, and then growing an epitaxial layer 46.

Next, as shown in FIG. 6 φ), using the same method as described in Example 3, the resist 46 is masked K[.

epitaxial layer 46. n embedded area 44. The epitaxial layer 43 and the n+ buried region 42 are etched by dry etching and wet etching using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid to form an opening 47.

Next, as shown in FIG. 6(0), after removing the resist 46, a dielectric film 48, typically a silicon oxide film, is formed on the surface of the opening 47, and polycrystalline silicon 49 is formed inside the opening. Embed.

According to this embodiment, by providing a plurality of wide horizontal grooves connected to narrow vertical grooves, the total area inside the grooves can be dramatically increased, and the storage capacity can be greatly reduced. A large capacitor can be obtained.

In this embodiment, a trench capacitor that is small and has a large storage capacity has been described, but it is possible to configure a dynamic memory in which a switching transistor for charging and discharging charge is integrated into the capacitor. Further, even if the cell area of this dynamic memory is made small, a sufficiently large storage capacity can be ensured.

Effects of the Invention The present invention provides a side wall opening wider than the surface opening,
By using the inner wall as the electrode surface, storage capacity can be increased, and the amount of dry etching used to form the groove can be reduced, resulting in an excellent groove-type capacitor that has the effect of reducing damage to the substrate. It is possible.

[Brief explanation of the drawing]

FIG. 1 is a structural cross-sectional view of a cell of a conventional MOS dynamic memory, FIG. 2 is a structural cross-sectional view of a trench-type capacitor cell, and FIG. 3 is a structural cross-sectional view of a trench-type capacitor in the first embodiment of the present invention. 4(2L) to (f) are process cross-sectional views of the trench type capacitor in the second embodiment of the present invention, and FIG.
a) to ((1) is a cross-sectional view of the process in the third embodiment of the present invention, and FIGS. 6(a) to (0) are cross-sectional views of the process in the fourth embodiment. 21...・Silicon substrate, 22・Old・・Capacitor dielectric film% 23・・・Polycrystalline silicon, 42・
...High concentration N buried region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4 ((L) Figure 4 (d,) (C) ?X Figure 5

Claims (5)

[Claims] (1) The groove opening provided on the surface of the semiconductor substrate, at least a part of which has a width wider than the surface of the sidewall, and a dielectric film formed on the surface of the groove opening of the semiconductor substrate. and a conductive film connected to the dielectric film and buried inside the trench opening, wherein the semiconductor substrate and the conductive film serve as electrodes, and the dielectric film serves as a storage capacitor. A semiconductor device characterized by comprising: (2) A patent claim comprising a capacitor whose storage capacitance is a dielectric film formed on the surface of the groove opening, and a switching transistor that charges and discharges charge in the capacitor, constituting a dynamic memory. range 1
1. Semiconductor device described in Section 1. (3) forming a first opening in a predetermined region of a semiconductor substrate; forming an etching-resistant coating on a surface of the semiconductor substrate and a side surface of the first opening; and forming a bottom surface of the first opening; etching the semiconductor substrate to form a second opening having a wider width than the first opening; removing the etching-resistant coating; and etching the first opening and the second opening. A method for manufacturing a semiconductor device, comprising the steps of: forming a dielectric film on the surface of the opening; and burying a conductive film inside the first opening and the second opening. . (4) A first opening having an opening area narrower than the area of the high concentration N^+ buried region is formed in the surface of the semiconductor substrate having the high concentration N^+ buried region in the lower part thereof. A step of etching and forming until reaching the ^+ buried region, and selectively etching the high concentration N^+ buried region to form a second opening having a width wider than the first opening. and forming a dielectric film on the surfaces of the first opening and the second opening, the dielectric film forming a storage capacitor of a capacitor. Method of manufacturing the device. (5) A first opening having an opening area narrower than the area of the high concentration N^+ buried regions in a semiconductor substrate having a plurality of vertically arranged high concentration N^+ buried regions in its lower part; forming a portion between the semiconductor substrate and the high concentration N^+ buried region and between the high concentration N^+ buried regions, and selectively etching the plurality of high concentration N^+ buried regions. a step of forming a plurality of second openings having a width wider than the first opening; and a step of forming a dielectric film on the surfaces of the first opening and the plurality of second openings. A method of manufacturing a semiconductor device, comprising: the dielectric film forming a storage capacity of a capacitor.