JPS6132533A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6132533A
JPS6132533A JP15437584A JP15437584A JPS6132533A JP S6132533 A JPS6132533 A JP S6132533A JP 15437584 A JP15437584 A JP 15437584A JP 15437584 A JP15437584 A JP 15437584A JP S6132533 A JPS6132533 A JP S6132533A
Authority
JP
Japan
Prior art keywords
electrode
protrusion
semiconductor element
hole
film lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15437584A
Other languages
Japanese (ja)
Inventor
Kenzo Hatada
畑田 賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15437584A priority Critical patent/JPS6132533A/en
Publication of JPS6132533A publication Critical patent/JPS6132533A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent any defective connection due to expansion or warp from happening by a method wherein a photosetting or thermosetting resin is laid between an electrode of semiconductor element and a film lead provided with a bump on the opposing position to the electrode and formed of a hole or a recession in said bump region. CONSTITUTION:A bump 4 is formed on a position opposing to an electrode 2 of semiconductor element 1 of a film lead 3 coming into contact with said electrode 2. The plane of bump 4 coming into contact with the electrode 2 is irregularly formed while a hole is formed in an arbitrary position of the bump 4. Besides, the hole 5 and the gaps between irregular recessions are filled with photosetting or thermosetting resin 6 however, a conductive adhesive or alloy material with low melting point mixed with conductive material such as Ag, Au or C may be laid between the hole 5 only and the electrode 2.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体素子の電極パッドと外部回路とを簡便
に接続する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for easily connecting electrode pads of a semiconductor element and an external circuit.

従来例の構成とその問題点 近年、半導体素子を多数個用いるデバイス、機器の開発
が促進されてきている。例えば、メモリーカード、液晶
やELディスプレイパネル等があシ、これらは、いずれ
も多数個のIC,LSIを一定の面積を有する基板に、
高密度にしかも薄型に搭載しなければならない。これら
IC,LSIの実装手段として、フィルムキャリヤ方式
やフリップチップ方式が公知であるが、次の様な問題が
あるO 前記フィルムキャリヤ方式もフリップチップ方式のいず
れも半導体素子の電極パッド上に金属突起を形成するが
、フリップチップ方式においては、配線基板上の配線パ
ターンと前記半導体素子の金属突起とを位置合せし、加
熱せしめて、半田づけ固定するものである。したがって
フリップチップ方式の場合は、電気的接続と配線基板上
への半導体素子の固定とを前記半田づけ固定した位置で
行なうもので、外部からの熱や機械的歪によシ配線基板
が膨張したシそったシした場合には、前記半田づけ位置
が強固に固定されているので、その変化に充分に対応で
きなくなシ、接続部や半導体素子自体の破損をまねいて
いた。
2. Description of the Related Art Conventional configurations and their problems In recent years, the development of devices and equipment that use a large number of semiconductor elements has been accelerated. For example, there are memory cards, liquid crystal and EL display panels, etc., which all have a large number of ICs and LSIs mounted on a substrate with a certain area.
It must be mounted in a high-density yet thin design. The film carrier method and the flip chip method are well known as mounting means for these ICs and LSIs, but they have the following problems: Both the film carrier method and the flip chip method have metal protrusions on the electrode pads of the semiconductor element. However, in the flip-chip method, the wiring pattern on the wiring board and the metal protrusion of the semiconductor element are aligned, heated, and fixed by soldering. Therefore, in the case of the flip-chip method, the electrical connection and the fixing of the semiconductor element on the wiring board are performed at the soldered and fixed position, and the wiring board is not subject to expansion due to external heat or mechanical strain. In the case of warping, since the soldering position is firmly fixed, the soldering position cannot be sufficiently accommodated to the change, leading to damage to the connecting portion or the semiconductor element itself.

また、フィルムキャリヤ方式においては、半導体素子上
の金属突起とフィルムリードとを接続し、前記フィルム
リードを配線基板の配線パターンと接続するため、前述
した、配線基板のそシや膨張等の変化に充分に対応でき
るものの、半導体素子の電極上に金属突起を形成しなけ
ればならない。
In addition, in the film carrier method, metal protrusions on the semiconductor element and film leads are connected, and the film leads are connected to the wiring pattern of the wiring board. Although this can be fully coped with, metal protrusions must be formed on the electrodes of the semiconductor element.

このために、半導体素子の歩留シを低下せしめたり、製
造コストを高価にしていた。前記金属突起を形成するこ
とは、前記フリップチップ方式の場合でも同一であり、
同一の問題があった。
For this reason, the yield of semiconductor devices has been reduced and manufacturing costs have been increased. Forming the metal protrusion is the same in the case of the flip chip method,
Had the same problem.

ところで、本発明者は、半導体素子の電極と回路基板の
配線パターンの接続において、半導体素子の電極上忙は
何らの処理をすることなく、孔もしくは凹部を形成した
突起を有するフィルムリードを前記電極に圧接し、これ
を樹脂材で固定することに着目することにより、接続部
の膨張やそシを吸収できこれにより接続不良やコスト高
を一掃できるということが判明した。
By the way, the inventor of the present invention has discovered that in connection between the electrodes of a semiconductor element and the wiring pattern of a circuit board, a film lead having a protrusion with a hole or a recess is connected to the electrode without performing any processing on the electrode of the semiconductor element. It has been found that by focusing on pressure-welding and fixing this with a resin material, expansion and distortion of the connection part can be absorbed, thereby eliminating connection failures and high costs.

発明の目的 本発明はこのような従来の問題に鑑み1回路基板の膨張
やそシに対応し接続不良の発生しない、安価な接続方法
を提供することを目的とする。
OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide an inexpensive connection method that can cope with expansion and distortion of one circuit board and prevents connection failures.

発明の構成 本発明は、半導体素子の電極と対応する位置に突起を有
し、かつ前記突起領域に孔もしくは凹部を形成したフィ
ルムリードとを光硬化性もしくは熱硬化性樹脂を介在さ
せて、圧接・固定するととによ多接続する構成である。
Structure of the Invention The present invention provides pressure bonding between a film lead having a protrusion at a position corresponding to the electrode of a semiconductor element and a hole or a recess formed in the protrusion area, with a photocurable or thermosetting resin interposed.・It has a structure that allows multiple connections when fixed.

実施例の説明 第1の実施例を第1図で説明する。Description of examples A first embodiment will be explained with reference to FIG.

フィルムリード3の半導体素子1の電極2に対応した位
置に突起4が形成され、これが半導体素子1の電極2に
接している。フィルムリード3の突起4は半導体素子の
電極と接する面に凹凸が形成され、更に突起4の任意の
位置に孔6が形成されている。更にまた、孔6および突
起面の凹凸の隙間には光硬化性樹脂もしくは熱硬化性樹
脂6が充填されているものであるが、孔6のみに導電性
物質例えば、Ag 、 Au 、 Cを混在させた導電
性接着剤あるいは低融点の合金材料等を介在させても良
い。
A protrusion 4 is formed on the film lead 3 at a position corresponding to the electrode 2 of the semiconductor element 1, and is in contact with the electrode 2 of the semiconductor element 1. The protrusion 4 of the film lead 3 has an uneven surface formed in contact with the electrode of the semiconductor element, and furthermore, a hole 6 is formed at an arbitrary position of the protrusion 4. Furthermore, although the holes 6 and the gaps between the unevenness of the protruding surface are filled with a photocuring resin or thermosetting resin 6, a conductive material such as Ag, Au, and C is mixed only in the holes 6. A conductive adhesive or a low melting point alloy material may also be used.

この様な構成は第2図の方法によって実現できる。半導
体素子1の電極2上に光硬化性樹脂もしくは熱硬化性樹
脂6を塗布しておく、これに、先端に突起4を形成し、
かつ孔6と少なくと゛も表面に凹凸を有するフィルムリ
ード4を位置合せしく第2図a)、ツール7により加圧
し、光または熱8を加える。これにより光硬化性樹脂も
しくは熱硬化性樹脂6は硬化し、フィルムリードの突起
と半導体素子の電極は圧接された状態で固定され、電気
的導通を得るものである(第2図b)。
Such a configuration can be realized by the method shown in FIG. A photocurable resin or thermosetting resin 6 is applied on the electrode 2 of the semiconductor element 1, and a protrusion 4 is formed on the tip thereof.
Then, the holes 6 and the film lead 4 having at least an uneven surface are aligned (FIG. 2a), and pressure is applied with a tool 7, and light or heat 8 is applied. As a result, the photocurable resin or thermosetting resin 6 is cured, and the protrusion of the film lead and the electrode of the semiconductor element are fixed in pressure contact, thereby obtaining electrical continuity (FIG. 2b).

この様な構成によれば孔には厚く樹脂が充填されるため
突起と半導体素子の電極とは強固に固定され、かつ突起
の表面の無数の凹凸で半導体素子の電極と接するため、
この界面での接触抵抗を著しるしく低下させることがで
きる。更にまた、凹凸の無数の隙間忙介在した樹脂もま
たフィルムリードと電極とを固定する役目をするもので
ある。
With such a configuration, the hole is filled with a thick resin, so that the protrusion and the electrode of the semiconductor element are firmly fixed, and the numerous unevenness on the surface of the protrusion makes contact with the electrode of the semiconductor element.
The contact resistance at this interface can be significantly reduced. Furthermore, the resin interposed in the numerous uneven gaps also serves to fix the film lead and the electrode.

更にのべれば、前記樹脂は電極2の表面を覆うため、外
部からの腐蝕性溶液の浸入を防止できる効果もある。
Furthermore, since the resin covers the surface of the electrode 2, it also has the effect of preventing corrosive solution from entering from the outside.

また、孔6に導電性物質を充填させれば、接続抵抗を著
しるしく低減できるばがりでなく、熱膨張等によ知フィ
ルムリード3の突gaと半導体素子の電極2との境界で
接続が離れたとしても、孔6に充填された導電性物質は
電極面に接合された寸ま、導電性物質自体が膨張するか
ら、接合が破かいされることがない。
Furthermore, if the holes 6 are filled with a conductive substance, not only can the connection resistance be significantly reduced, but also the connection can be made at the boundary between the protrusion of the film lead 3 and the electrode 2 of the semiconductor element due to thermal expansion, etc. Even if the electrodes separate, the conductive material filled in the hole 6 expands to the extent that it is bonded to the electrode surface, so the bond will not be broken.

第3図は第2図の実施例である。FIG. 3 is an embodiment of FIG. 2.

フィルムリードaの突起4部分に凹部6′ を形成し、
これに光硬化性樹脂もしくは熱硬化性樹脂あるいは導電
性物質6を充填した構造である。効果は第1の実施例と
同一である。
A recess 6' is formed in the protrusion 4 of the film lead a,
This has a structure in which a photocurable resin, a thermosetting resin, or a conductive substance 6 is filled. The effect is the same as the first embodiment.

またフィルムリードの突起の形状は第4図aに示す様に
、可撓性フィルム10上に形成されたフィルムリード3
の先端部のみをエツチング加工して残存させ突起4を形
成するが、孔6は前記エツチング加工の段階で形成する
こともできる。更に(b)図はフィルムリード3の先端
にフィルムリード3の材質とは異なる凹部6′を有する
突起4′を接合したもので、この様な構成であれば、(
−)図の実施例の如く、フィルムリード3自体をエツチ
ング加工する必要がないため、材料の無駄がなく製造コ
ストが安価になる。
Further, the shape of the protrusion of the film lead is as shown in FIG.
Although only the tip of the protrusion 4 is etched and left to form the protrusion 4, the hole 6 can also be formed at the etching step. Furthermore, in the figure (b), a protrusion 4' having a recess 6' different from the material of the film lead 3 is joined to the tip of the film lead 3. With such a structure, (
-) Unlike the embodiment shown in the figure, there is no need to perform etching on the film lead 3 itself, so there is no waste of material and manufacturing costs are reduced.

さらに他の実施例を第3図で説明する。フィルムリード
3の突起4が形成された反対面に可撓性フィルム10′
を有する構造であって、少なくとも前記半導体素子1を
覆う如く可撓性フィルム10′が形成されるものである
。この様な構成であれば、可撓性フィルム10’にフィ
ルムリード3を突出すための開孔部を形成する必要がな
いばかりか、半導体素子1の上面を可撓性フィルム10
’が覆っているから、半導体素子と可撓性フィルムの間
に保護樹脂12を充填すれば、著しるしく信頼性の高い
半導体装置を得ることができるものである。
Still another embodiment will be explained with reference to FIG. A flexible film 10' is placed on the opposite side of the film lead 3 on which the protrusion 4 is formed.
In this structure, a flexible film 10' is formed to cover at least the semiconductor element 1. With such a configuration, not only is it not necessary to form an opening in the flexible film 10' for protruding the film lead 3, but also the upper surface of the semiconductor element 1 is not connected to the flexible film 10'.
', therefore, by filling the space between the semiconductor element and the flexible film with the protective resin 12, it is possible to obtain a semiconductor device with significantly high reliability.

発明の効果 1 半導体素子の電極と接するフィ、ルムリードの先端
に突起と前記突起に凹部または孔を設渉た構成によシ、
前記突起の凹部または孔に厚く樹脂を充填できるため、
前記充填した樹脂′の陰暦強度を著しるしく高める事が
できる。このために前記半導体素子の電極とフィルムリ
ードとめ、前記フィルムリードが半導体素子の端部に接
触し、電気的接続不良を発生することかない。
Advantageous Effects of the Invention 1 Due to the structure in which a protrusion is provided at the tip of the filler lead in contact with the electrode of the semiconductor element, and a recess or hole is provided in the protrusion,
Since the recess or hole of the protrusion can be filled with a thick resin,
The lunar strength of the filled resin can be significantly increased. For this reason, the electrode of the semiconductor element and the film lead are connected, and the film lead does not come into contact with the end of the semiconductor element, thereby preventing an electrical connection failure from occurring.

また、本発明の構成では、フィルムリードの突起に形成
されている凹部もしくは孔は、前記突起の中央部領域に
設けられるものであるから、電極と接する突起の中心領
域で強固に圧接する状態になるから、電極との接触界面
は、はぼ全域にわたり、均一な加重を得ることになる。
Furthermore, in the configuration of the present invention, the recess or hole formed in the protrusion of the film lead is provided in the central region of the protrusion, so that it is firmly pressed against the central region of the protrusion that contacts the electrode. Therefore, a uniform weight is obtained over almost the entire contact interface with the electrode.

このため、回路基板のソリや歪が発生しても、前記フィ
ルムリードの機械的な伸縮も加味され、安定で信頼度の
高い接続を得ることかできるものである。
Therefore, even if the circuit board warps or distorts, the mechanical expansion and contraction of the film lead is taken into consideration, and a stable and highly reliable connection can be obtained.

さらにまた突起面の凹凸は、電極との接触点を著しるし
く増加させるものであるから、接触抵抗を低下さす効果
を有する。
Furthermore, since the unevenness of the protruding surface significantly increases the number of contact points with the electrode, it has the effect of reducing contact resistance.

2 また、前記突起の孔もしくは凹部に導電性物質を充
填すれば、接触抵抗を著しるしく下げ信頼度の高い接続
を得ることができるし、前記導電性物質が、半導体素子
の使用温度範囲内で柔軟性のある低融点合金材料等であ
れば、突起と電極の接触界面が回路基板のソリや歪によ
って離れたとしても、前記低融点合金材料が、柔軟に対
応するために絶えず、安定な接続を継続できるものであ
る。
2 Furthermore, if the holes or recesses of the protrusions are filled with a conductive substance, the contact resistance can be significantly reduced and a highly reliable connection can be obtained. If the contact interface between the protrusion and the electrode is separated due to warping or distortion of the circuit board, the low melting point alloy material will be able to respond flexibly and constantly maintain a stable state. The connection can be continued.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例で、フィルムリードの突
起に孔を設けた構成の断面図、第2図(a)。 (b)は第1の実施例の製造方法を示す工程断面図、第
3図は本発明の第2の実施例でフィルムリードの突起の
凹部を設けた構成の断面図、第4図(a)。 −)は本発明のフィルムリードの断面形状を示す断面図
、第6図は本発明の第3の実施例で、フィルムリードの
反対面に可撓性フィルムを形成した構成の断面図である
。 1・・・・・・半導体素子、2・・・・・・電極、3・
・・・・・フィルムリード、4・・・・・・突起、6・
旧・・孔もしくは凹部。 代理人の氏名 弁理士 中 尾 敏 男 線か1名第3
図 第5図
FIG. 1 shows a first embodiment of the present invention, which is a cross-sectional view of a structure in which holes are provided in the protrusions of the film lead, and FIG. 2(a). (b) is a process cross-sectional view showing the manufacturing method of the first embodiment, FIG. 3 is a cross-sectional view of a structure in which a concave portion is provided for the protrusion of the film lead in the second embodiment of the present invention, and FIG. ). -) is a cross-sectional view showing the cross-sectional shape of the film lead of the present invention, and Fig. 6 is a cross-sectional view of a third embodiment of the present invention, in which a flexible film is formed on the opposite side of the film lead. 1... Semiconductor element, 2... Electrode, 3...
...Film lead, 4...Protrusion, 6.
Old: hole or recess. Name of agent: Patent attorney Toshi Nakao (3rd person)
Figure 5

Claims (3)

【特許請求の範囲】[Claims] (1)半導体素子の電極と対応する位置に突起を有し、
かつ前記突起領域に孔もしくは凹部を形成したフィルム
リードの前記突起と、前記半導体素子の電極との間に光
硬化性もしくは熱硬化性樹脂を介在させ、接合したこと
を特徴とする半導体装置。
(1) Having a protrusion at a position corresponding to the electrode of the semiconductor element,
A semiconductor device, characterized in that a photocurable or thermosetting resin is interposed between the protrusion of the film lead in which a hole or a recess is formed in the protrusion region and the electrode of the semiconductor element, and the protrusion is bonded to the protrusion.
(2)突起領域の孔もしくは凹部が導電性物質によって
充填されることを特徴とする特許請求の範囲第1項記載
の半導体装置。
(2) The semiconductor device according to claim 1, wherein the hole or recess in the protrusion region is filled with a conductive material.
(3)突起を有するフィルムリードの前記突起の反対面
に可撓性フィルムを形成したことを特徴とする特許請求
の範囲第1項記載の半導体装置。
(3) The semiconductor device according to claim 1, wherein a flexible film is formed on the opposite side of the protrusion of the film lead having a protrusion.
JP15437584A 1984-07-25 1984-07-25 Semiconductor device Pending JPS6132533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15437584A JPS6132533A (en) 1984-07-25 1984-07-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15437584A JPS6132533A (en) 1984-07-25 1984-07-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6132533A true JPS6132533A (en) 1986-02-15

Family

ID=15582778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15437584A Pending JPS6132533A (en) 1984-07-25 1984-07-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6132533A (en)

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