JPS613222A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the occupation area of a timer circuit by providing the >=2 2nd buses connected to the internal bus of a microcomputer, and connecting a constant register, etc., to one bus and a counter register, etc., to the other. CONSTITUTION:A single-chip microcomputer MPU consists of a CPU1, ROM2, RAM3, timer circuit 5, input/output port 6, etc., which are connected mutually through the internal bus 7. For this purpose, a time-sharing (TSS) bus 8 is provided as the 2nd bus in the timer circuit 5 and connected to said internal bus 7 through a switching circuit 9 which is controlled with the signal from a control part 10. This TSS bus 8 consists of three buses 8a-8c and forms two sequences of buses; the counter register CNT-REG and constant register CST-REG are connected through gates Ga-Gc respectively and a common counter CNT and a comparator CMP are also connected, so that substantially three timers are put in operation simultaneously.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing technology and a technology that is particularly effective when applied to the configuration of a timer in a data processing system. Regarding technology.

[Background Art] A timer in a conventional microcomputer is, for example, a counter C that counts a clock φ, as shown in FIG.
NT and the microprocessor C via the internal bus BUS.
A register REG that holds desired time data given from the PU etc. is constantly compared with the contents of this register REG and the contents of the counter CNT. The comparator CMP outputs the output to the comparator CMP. (For example, "Hitachi Microcomputer System 48MC86800C Manual" published by Hitachi, Ltd. in September 1982)
(See page 31). Alternatively, in addition to these, in synchronization with the falling or rising edge of a signal supplied from the outside,
A register (input capture register) for reading and holding the current contents of the counter CNT may be provided (see page 28).

However, in recent years, as microcomputers have become more sophisticated, more timers have become necessary. Therefore, when a timer having the above configuration is used as a timer for a microcomputer, if it is desired to increase the number of timers, it is necessary to provide corresponding numbers of counters CNT, registers REG, and comparators CMP that constitute the timers. As a result, there is a problem in that the number of counters and comparators constituting the timer increases, the area occupied by the circuit increases, and the chip size increases.

[Object of the Invention] An object of the invention is to reduce the chip size of a microcomputer having multiple timers by reducing the accuracy (resolution) of the timer.
The objective is to provide a technology that can reduce the size of the image without sacrificing it.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, two or more secondary buses connected to the internal bus of the microcomputer are provided, and these second
A plurality of constant registers and a common comparator are connected to one of the buses, and a plurality of counter registers and a common counter are connected to the other second bus. Used in a time-division manner, the data in the counter registers is sent one after another to a common counter, incremented or decremented, and then returned to the original counter register, and the contents of each constant register corresponding to the above counter registers are used. The number of counters and comparators, which have a large number of components, can be reduced by sending the data one after another to a common comparator and comparing it with the contents of the counter, and outputting a timer signal when they match, thereby realizing multiple timer functions. The present invention achieves the above object of reducing the chip size of a microcomputer having a plurality of timers without reducing the precision (resolution) of the timers.

The present invention will be described in detail below along with examples.

[Example 1] Fig. 2 shows an example in which the present invention is applied to a single-chip microcomputer. is formed.

The single-chip microcomputer MPU of this embodiment includes, but is not particularly limited to, a microprocessor (hereinafter referred to as CPU) 1 that controls an internal execution unit etc. according to a program, and a ROM (read・Only memory) 2, mainly CPU
It consists of a RAM 3 providing a work area for I, a timer circuit 5, an input/output capotro, etc., and these are connected to each other via an internal bus 7.

The CPtJ1 is, but is not particularly limited to, a program counter that holds the address of the next instruction or data to be read;
Various registers such as an instruction register from which program instructions are sequentially fetched, a micro ROM in which a micro program is stored, a control decoder and an accumulator that decode micro instructions read from this micro ROM and form a control signal; It is composed of an ALU (arithmetic logic unit) and the like.

In this embodiment, a TSS bus (time division bus) 8 is provided in the timer circuit 5 as a secondary second bus, and this TSS bus 8 is connected to the internal bus 7 via a switching circuit 9. Being connected. The switching circuit 9 is controlled by a signal output from a control section 10 provided for controlling the timer circuit 5.

Furthermore, the single-chip microcomputer MPU divides the oscillation signal O8C supplied from the outside to provide a system clock signal φ1. A frequency dividing circuit 11 is provided which forms φ2 and supplies it to the CPUI and the like. The above control section 10
, a clock signal φ0 having a higher frequency than the clock signal φ1゜φ2 extracted from the previous stage of the frequency dividing circuit 11 is used.
is supplied to the timer circuit 5 based on the clock signal φ0.
The various registers and counters (described later) that make up the TSS bus 8 are operated at appropriate timings, and the TSS bus 8 is used in a time-sharing manner to form and output control signals that realize multiple timer functions. .

The timer circuit 5 is constructed as shown in FIG. 3, for example.

Although not particularly limited, this embodiment shows one having three timers.

As shown in the figure, the TSS bus 8 connected to the main internal bus 7 on the system side is composed of three TSS buses 8a to 8c connected via gates 9a to 9C, and has two series as a whole. It is like having a bus. For these TSS buses 8a to 8c, three counter registers C that hold the count value of a counter CNT, which will be described later, are provided.
NT-REG1 to CNT REGs and 3 that holds data for a predetermined time written according to instructions from the CPU.
constant registers C8T REG, ~C3T-REG
3 are connected through gates Ga-Gc, respectively.

Further, the TSS buses 8a to 8c are provided with the three counter registers CNT-REG, to CNT-REG.
A counter CNT common to s and three constant registers C
A common comparator CMP is connected to 3T-REG and CST-REGs.

Moreover, in this embodiment, the counter register CNT
REG1 to CNT-REG3 and common counter C
NT is connected to the first series TSS bus 8a through gates Ga1 to Ga4, respectively, and is connected to a constant register CST.
-RE G1 to C:5T-REG3 and common comparator CMP are connected to the second series TSS bus 8b via gates Gb and -Gb+, respectively. Furthermore, each of the above registers CNT-RE G1 to CNT-RE
G,, C3T-RE G s~CS T-RE G
s and common counter CNT are each gate G c 1
~Qe7 is connected to the TSS bus 8c.

Although the common counter CNT is not particularly limited, here it is constituted by an incrementer, and the common comparator CMP has a buffer function for holding data (contents of a constant register) given via the TSS bus 8b, The flower data and the contents of the common counter CNT are compared.

The timer circuit configured as described above has T
Three timers can be operated simultaneously using the SS buses 8a to 8c&.

Moreover, in this embodiment, the system clock φ1. A clock φ0 having a frequency four times the frequency of φ2 is supplied to the control unit 10, and the counter CNT and comparator CMP constituting the timer circuit 5 are
It is set to run at four times the frequency of the system clock.

That is, at a certain timing t as shown in FIG.
a1 and Ga4 are opened and the first counter register C
The contents of NT-REGI are output to the TSS bus 8a and supplied to the counter CNT. Then, after 1 is added to that value, gates Qc7 and Gcl are opened and the value of counter CNT is returned to the original counter register CNT-RE.
He is placed in the G.I.

Meanwhile, in parallel with the above operation, gates Gby and Gb4 are opened at the same time as gates Ga1-Ga4, and the contents of the first constant registers C3T-REGl are outputted to TSS)<8b and supplied to the comparator CMP. Ru. Comparator CMP is supplied with constant register C, 5T-REG
The contents of , are held and compared with the count value added by the counter CNT at that time.

At the next timing t2, gates Qa2 and G a
4 is opened and the second counter register CNTRE G
After the contents of 2 are supplied to the counter CNT through the TSS bus 8a and incremented by 1, the gate Gc7 is opened.
) Gc3 and the original register C via TSS bus 8c
N T -RE G x and the gate G
b2 and Gb4 are opened and the second constant register CST
-The contents of RE G 2 are supplied to the comparator CMP through the TSS bus 8b and compared with the value of the counter CNT at that time.

Furthermore, at the next timing t3, the gate Ga3 is opened and the contents of the third counter register CNT-REG3 are supplied to the counter CNT through the TSS bus 8a.
is added and then returned to the original register via gate GC3, and the third constant register CNT R
The contents of EG3 are sent to comparator C via TSS bus 8b.
It is supplied to MP and compared with the value of counter CNT.

In this way, by using the TSS buses 8a and 8b in a time-divisional manner, three counter registers CNT-RE G 1 to 1 are processed during one system clock cycle.
The contents of CNT-REG3 are incremented one after another, and constant registers C3T-REG, ~C3T-
It is compared with the contents of REG3. Then, constant registers C3T-REG, ~C3T set in advance by the CPU
- When the contents of REG3 and the contents of counter CNT match, it is assumed that a predetermined time has elapsed, and the comparator CMP
The timer output is supplied to the CPU and the like.

In this way, in the above embodiment, one counter CN
T effectively causes three timers to run simultaneously;
Three types of timer output can be obtained. Furthermore, when a match signal is output from the comparator CMP, the corresponding counter register is reset and starts counting time anew.

In the above embodiment, at timing tc of clock φ0 shown in FIG.
The current values of EGI to CNT REG3 can be read. In that case, for example, CP
An address decoder for decoding a predetermined address output from U1 is provided in the control section 10. Then, when the CPUI reads or writes the register in the timer circuit 5 based on the decoded signal, the control unit 1O supplies a control signal to the gates 9a to 9c to open the appropriate gates and connect the TSS bus. 8a to 8c may be connected to the internal bus 7 on the CPU side.

Furthermore, although the above embodiment is shown as having three timer functions, it is also possible to further increase the number of counter registers and constant registers to have four or more timer functions. be. In that case, in order to prevent the resolution of each timer, that is, the operating frequency, from decreasing,
System clock φ1. It is sufficient to use a clock having a higher frequency than the clock φ0, which has a higher frequency than φ2. In addition, if the resolution of the timer does not need to be reduced to some extent, the TSS bus should be set so that the register is operated once every two cycles of the system clock φ1 (φ2). It can be used in a time-sharing manner.

According to the above embodiment, since a common counter and a comparator are provided for the counter register and constant register that constitute each timer, it is necessary to realize the same number of timers compared to the configuration shown in FIG. The number of counters and comparators can be reduced. However, since each register can be configured with a smaller number of elements than a counter or a comparator, the area occupied by the entire timer circuit is reduced. This tendency becomes more pronounced as the number of timers is increased.

[Example 2] A second embodiment of the invention is shown in FIG.

In this embodiment, T S' provided in the timer circuit 5
Transmission (reception) registers 5-REG1 and 5-RE forming two serial input/output devices for S buses 8a to 8c
G2 and their common sick (shift register)
SFT and gates Ga6~Ga1° and Gc6~G
It is connected via C10. Then, transmit (receive) register 5-REG1゜5-REG2 and shifter SF
T connects the TSS buses 8a and 8C to a counter register CNTREG]~CNT- which constitutes a timer.
By using it in a time-divisional manner together with REG3, it is possible to perform multiple serial communications.

That is, in this embodiment, the contents of the counter registers CNT-REGI to CNT-REG3 constituting the timer are sequentially supplied to the counter CNT, incremented and incremented, and returned to the original registers, and then the transmission register S RE
The data of Gl is sent to the shifter SFT through the TSS bus 8a, shifted by 1 bit, and data of 1 bit 1~ is outputted.

Then, the shifted data is returned to the original register S-REG through the TSS bus 8C, and then the data in the second transmission register S-REG2 is transferred to the TSS bus 8C.
The data is sent to the shifter SFT through the bus 8a and shifted by one bit to output one bit of data, and the shifted data is returned to the original register 5-REG2. After that, the timer operation using the TSS buses 8a to 8c is started again. This allows serial data to be transmitted in parallel with the timer operation. Similarly, it is also possible to receive serial data.

In this way, by using the TSS buses 8a to 8C in a time-sharing manner, multiple timer functions and multiple serial communication functions are realized.

In this embodiment, two serial transmit (receive) registers 5-REG1.5-REG2 form one thick SF.
Since T is shared, the number of elements in the entire circuit is smaller than in the case where two serial input/output devices are configured separately, and the occupied area is reduced.

Moreover, in this embodiment, the timer and the serial input/output device are operated by using the same TSS buses 8a to 8C in a time-sharing manner, so the configuration of the control unit 10 is simplified and the overall occupied area is reduced. It has the advantage of having less

Further, in this embodiment as well, it is possible to provide more transmitting (receiving) registers to provide three or more serial communication functions. In that case, if you do not want to reduce the resolution and speed of the timer or serial input/output device, use the TSS buses 8d and 8e of different series as shown by the broken line in Figure 5.
[Effect] Two or more secondary buses connected to the internal bus of the microcomputer are provided, and one of these second buses has multiple constant registers and these A common comparator is connected to the second bus, and a plurality of counter registers and a common counter are connected to the other second bus. are sent to the above counter one after another, incremented or decremented, and then returned to the original counter register, and the contents of each constant register corresponding to the above counter register are sent one after another to a common comparator to calculate the contents of the counter. Since the timer signal is output when a match is made and multiple timer functions are realized, the number of counters and comparators, which have a large number of components, is reduced, which makes the timer circuit The occupied area is reduced, which allows the chip size of a microcomputer with multiple timers to be reduced/J% without reducing the accuracy (resolution) of the timer.
It has the effect of being able to

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although an incrementer is used as the common counter CNT, it is also possible to use a decrementer instead of the incrementer.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a single-chip microcomputer, which is the field of application that formed the background of the invention, but this invention is not limited thereto, and can be applied to It can also be used in peripheral LSIs such as I10 chips that constitute chip computers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a timer circuit in a conventional microcomputer system, and FIG. 2 is a block diagram showing an embodiment in which the present invention is applied to a single-chip microcomputer. FIG. 3 is a block diagram showing one embodiment of a timer circuit according to the present invention. FIG. 4 is an explanatory diagram showing an example of the operation timing of the timer circuit, and FIG. 5 is a block diagram showing another embodiment of the present invention. 1...-〇PU (microprocessor), 2...
・ROM (read only memory), 3...R
AM (Random Access Memory), 5...Timer circuit, 6...I/O port, 7...1st bus (internal path), 8.8a to 8e...2nd Bus (TB)
S bus) -9----switching circuit, -9a to 9C...
Gate, 10...control section, 11...branch circuit, CNT...counting means (counter), CMP
...compari 4-ta, CNT REGI~CNT
-REG, ... Counter register, C8'r -R
E G s~C5T REGa...constant register, S REGl-S REG2...transmission (reception) register, SFT...shifter.

Claims (1)

[Claims] 1. A second bus is connected to the first bus connected to the microprocessor that controls the system via a switching means, and the second bus includes a time setting bus. A plurality of constant registers for holding data, a comparator common to these constant registers, a counter register for holding the above constant registers and time data, and a common counting means for these counter registers are connected to each other, and time sharing is performed. Using the second bus, the data in each counter register is sequentially sent to the counting means and incremented or decremented, and then returned to the original counter register, and the data in each counter register corresponding to the counter register is sent to the counting means. Data characterized in that the contents of the constant register are successively sent to the common comparator and compared with the contents of the counting means, and each has a plurality of timer functions that output a signal when they match. Processing equipment. 2. Two or more series of second buses are connected to the first bus through switching means, and one of these second buses has a plurality of constant registers and a common comparator for them. A plurality of counter registers and common counting means are connected to the other second bus,
2. The data processing device according to claim 1, wherein a plurality of timer functions are implemented using the second bus in a time-division manner.