JPS6132145A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain high speed processing by providing required number of buses to a program controller to realize parallel transfer of data, and operating in parallel plural arithmetic circuits. CONSTITUTION:The program controller consists of a programmable connector 1 having a connecting function between an external input terminal and an internal arithmetic circuit and an arithmetic unit 10 executing the four rules. In obtaining a multiplication between a sum of I1 and I2 and a quotient of I3, I4, an addition command data is written into an arithmetic command register 11A by suing an address bus AB, a data bus DB and a write WR signal to function an arithmetic circuit 13 as an adder circuit. Further, a connection command data for a terminal 1 of the circuit 13 and an input terminal I1 is written in a connection command register 2A by using the AB, DB and WR signals. Similarly, an arithmetic/connection command is issued to an arithmetic circuit 14, parallel processing of division is executed and multiplication is executed in the arithmetic circuit 15.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a programmable controller, and in particular,
Related to parallel processing high-speed programmable controller.

[Background of the invention]

As an element whose logic can be freely changed, for example, as shown in the Technical Report of the Institute of Electronics and Communication Engineers (EC82-12, 1982/6), combinational logic expressed by a product-sum ring can be combined with logic memory and AND-OR. A constructed dynamic logic array has been reported.

However, using this method, it is difficult to construct a programmable controller (hereinafter referred to as PC) that can freely program operations such as first power, division, and relation generation.

[Purpose of the invention]

An object of the present invention is to provide a large number of arithmetic circuits that can operate in parallel;
The object of the present invention is to provide a parallel processing high-speed PC configured with a programmable connection device that arbitrarily connects the arithmetic circuits.

[Summary of the invention]

Current PCs and computers are of the Neumann type.

The Neumann type is a method in which a processing unit sequentially executes instructions stored in a storage device, and the hardware is simple, but it has the following problems.

The first is to read the instructions stored in the storage device,
It is difficult to parallelize the process because it is executed repeatedly after decoding. The second problem is that since instructions, data, etc. are transferred between the processing device and the storage device via a single bus, the data transfer speed is limited by the speed of the bus, that is, a bus neck occurs. Therefore, there is a limit to how high the speed can be increased. As a countermeasure to this problem, efforts have been made to increase the speed of circuit elements, but there are limits to this, so it has been desired to realize an effective parallel processing method.

The present invention focuses on the fact that conventional PCs transfer data via one bus, prepares the required number of buses, realizes parallel data transfer, and integrates multiple arithmetic circuits. By performing parallel operations, it is intended to realize a parallel processing high-speed PC.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 7.

FIG. 1 is a diagram showing the configuration of a PC according to the present invention. Reference numeral 1 denotes a programmable connection device, which has a connection function between arbitrary terminals, such as connection between an external input terminal 1 of a PC, for example, and an internal arithmetic circuit 13. Connection command registers 2A to 2G are registers that store connection commands between arbitrary terminals. A connection line 3 connects arbitrary terminals according to commands from the command registers 2A to 2G. 10 is an arithmetic unit that performs addition and
This is a device that performs division, multiplication, etc. 13 to 15 are additions/
Arithmetic command register II is an arithmetic circuit that performs division, multiplication, etc.
The calculation function is determined by A to IIC. IIA-IIC are arithmetic command registers which select and command the arithmetic functions of the arithmetic circuits 13-15. Engineering.

~■4 is an input signal of the PC 30, and 01 is an output signal.

AB is an address bus, BD is a data bus, and WR is a write timing signal, 2A to 2G.

This is a data write signal to 11A to IIC.

The operation will be explained using an example in which a PC is caused to execute the calculation shown in FIG. The contents of this operation can be expressed as a formula: In other words, the result of multiplying the sum of ■, and 12, and the quotient of engineering, and engineering 4 is obtained. In order to realize this operation, IIA~11G and 2A~2G
Specify the contents of.

First, add addition command data A to calculation command register IIA.
Write using B, DB, WR double signals.

This data is specified as a numerical value, for example, 3. If this command is an addition command, the arithmetic circuit 13 will function as an addition circuit. Next, signal lines are connected to the arithmetic circuit 13. Completed connection with the terminals of the arithmetic circuit 13,
It is necessary to connect the terminals. Therefore, the connection command data for the terminal 1 of the arithmetic circuit 13 and the input terminal check is written into the connection command register 2A using the AB, DB, and WR multiplied signals.

Similarly, according to FIG. 2, a desired arithmetic function can be programmed by specifying arithmetic circuit functions and connection commands to the arithmetic command register and connection command register.

A distinctive feature of a PC configured in this manner is that signal transmission and arithmetic operations are executed in parallel, so high-speed processing can be achieved. That is, the input signals 4 to 4 are simultaneously applied to the arithmetic circuits 13.14, the arithmetic circuits 13.14 simultaneously start arithmetic operations, and the arithmetic results are outputted as the output signal O8 via the arithmetic circuit 15. . In this way, a parallel processing high-speed PC can be realized.

Next, the programmable connection device 1, which is a component of the PC of the present invention, and the calculation bag fi! 10 will be explained in detail.

FIG. 3 shows the functionality of the programmable connection device.

1 is a programmable connection device; 2 is a connection command register that stores connection commands between input terminals and output terminals;

3 is the input terminal X, - according to the contents of the connection command register 2.
A connection line connecting X3 and output terminals 70 to 73 is shown.

The register 2 consists of a plurality of registers, and each register has an address bus ABO, ABI for register selection, and a data bus DBO for data application.

DBI and data write signal line WR are connected.
Connection commands between input terminals X0 to X3 and output terminals 70 to 73 can be written therein. As shown in FIG. 1, the contents of the connection command register 2 are (Xa, 'y-): X
Connect a and Yo (X,, Y,): X, and Y.

(Xs, Ya): X12 and y, n(Xa
-Ys): Xt and Y3, the input and output terminals of the connection line 3 are connected in accordance with the connection command indicated by the register 2 as follows.

X s Y a X, -Y.

Xl2-Y.

1-Y3 This means that the signal applied to input terminal X3 is immediately output to Y0, and similarly, the signal applied to Xo = Xs+e It is shown that. That is, it means that signals can be transferred in parallel.

FIG. 4 is a detailed diagram of the programmable connection device. 4 is a buffer that takes in an input signal, and 5 is an inverter that receives the output signal of register 2 and inverts the signal. 6 is an AND-OR circuit that selects one of the input signals X0 to X4 based on the signals of the input terminals X0 to X4 inputted via the buffer 4 and the connection command signal applied from the register 2 via the inverter 5. It is a gate.

In the connection command register 2, a connection command between the input terminals X0 to X4 and the output terminals 70 to 74 can be written. Assume that the following data is written in the connection command register 2.

The &O connection command is X s = Y o and the connection data is 11 in binary. This is output terminal Y0 input terminal X3
The connection data, which is the actual content of the connection command register, is the binary data 11 corresponding to the input terminal X3. Output terminal Y
The AND-OR gate 6 connected to
Signals 0 to X4 are applied via the buffer 4, and connection data 11 of the connection command register 2 is applied to the inverter 5.
Signals A, A, B, and B are applied to the AND-OR gate. The logic of the AND-OR gate is written as follows.

Ya = A B Xo + A B XI + ABX, +
A B
- Group - (3) Therefore, the signal of the input terminal X3 is outputted to the output terminal Y0. In other words, as a signal,
This means that the input terminal X3 and the output terminal Y0 are connected.

Similarly, Xa-Yt-XQY.

Xl'j and Y3 are connected.

In this way, this programmable connection device can freely connect the input terminal and the output terminal by writing a connection command in the connection command register 2.

FIG. 5 shows a programmable connection device that is a modification of the one shown in FIG.

In FIG. 4, one connection line corresponds to a connection command register. The example in FIG. 5 shows a case where two connection lines correspond to one connection command. That is, it attempts to connect two wires at a time.

Next, the operation will be explained. 7 is a programmable connection circuit, 2
3 is a connection command register, 3 is a connection line, 4 is a buffer, 5 is an inverter, and 6 is an AND-OR gate. Assume that the following data has been written and sent to the connection command register in the same manner as described above.

Writing the logic of output Y 00 * Y 01 as a formula is Yoo
==AXoo +AX1G ・−・”・(
4) Substituting connection data A=1 into equation (4) yields Yoo
= xlO−°°“°0°゛8 (shi) Similarly, Y o 1 ” A X ot 10A X 11
・・・・・・(6) Connection data A=1 is expressed as (
6), YOI=Xll
...'...(7) That is, the contents of one connection register, terminals XIO and Y. This means that the connection between 0 Xll and Yol has been established.

Although FIG. 5 shows an example of two connections using one connection command register, this can easily be expanded to three or more connections.

FIG. 6 is a block diagram of an arithmetic unit that is a component of a PC.

The function of a calculation device is to input data and output calculation results. Reference numeral 11 denotes an arithmetic command register, and the function of the arithmetic device is determined by the contents of this register. A decoder 12 controls buffer gates 16 to 18, which will be described below, according to the contents of the operation register. 13 to 15 are arithmetic circuits.

16 to 18 are buffer gates. The buffer gate selects the output signals of the arithmetic circuits 13 to 15 based on the gate signals 19 to 21 from the arithmetic command register 12 and transmits the selected signals to the output O1. Next, the overall operation of this circuit will be explained.

The calculation command register 11 includes a calculation command register selection address bus AB0. AB, data bus D for data application
B,,DB, are connected to a data write signal line WR, and are configured so that data can be written thereto. Assuming that the data value is 3 (binary number 11), this data is applied to the decoder 12, and the decoder 12 outputs a signal only to the output terminal 3 based on the input data, and outputs a signal to the buffer gate 16 via the gate signal line 19. is applied, and only buffer gate 16 opens its gate. Therefore, the calculation input signals I,,I of the calculation device. is calculated by the calculation circuit 13, and the result is outputted to the O8 terminal via the buffer gate 16. That is, by writing data 3 to the arithmetic register 11, the arithmetic device 10 functions as an adding device.

Similarly, the contents of the calculation command register can be divided by 2 and multiplied by 1.

Figure 7 shows the programmable connection device and the P
1 is a configuration diagram of a large-scale PC combining C. 30 is P
Cll is the programmable connection device mentioned above. I1
1 to 1, N is the input signal of the PC, which should be connected to the PC in advance.Oll'' 04 N is the output signal of the programmable connection circuit, which should also be connected in advance.Similarly, between the PC and 20, connect it to the PC in advance. Fixed wiring is also established between the PC 30 and the programmable connection device as shown in Fig. 7.A large-scale PC configured in this way can function as one parallel processing PC.First, the functions of the PC 30 are as shown in Fig. 1. .

It is programmable as explained in FIG.

The connection between the adjacent terminals 20 in FIG. 2 can also be made by a programmable connection device that can freely connect the terminals, as explained in FIGS. 3 to 5. Thirdly, it is necessary to connect non-adjacent PCs, but this can also be done using the programmable connection device described in FIGS. 3 to 5.

With the above, a large-scale parallel processing PC can be realized.

Note that the data handled by the PC of the present invention can be either - bit or multiple bits.

〔Effect of the invention〕

According to the present invention, a parallel processing PC can be realized, and the processing speed of the PC can be increased in proportion to the number of processing items to be executed in parallel. In practical terms, compared to the processing speed of a conventional PC, 1
A speed increase of approximately 00 times is easily achievable, and the application of the product can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a PC according to the present invention, FIG. 2 is a diagram explaining the program procedure of the PC, FIG. 3 is a diagram explaining a programmable connection device, and FIG. 4 is a diagram showing the configuration of a scale PC made with programmable connections.

Claims (1)

[Claims] 1. In a programmable controller that inputs a signal from a controlled object and outputs the result of signal processing to the controlled object, a large number of controllers that automatically output a specified output signal when an input signal is applied. between an arithmetic device consisting of an arithmetic circuit capable of parallel operation and the arithmetic circuit, between the arithmetic circuit and the input terminal of the programmable controller, between the arithmetic circuit and the output terminal of the programmable controller, and between the arithmetic circuit and the programmable controller; a connection device that can be arbitrarily connected between the input terminal and output terminal of the programmable
A plurality of input signals of the controller are connected to the programmable
A programmable controller comprising: a device for transmitting information in parallel to the plurality of arithmetic circuits inside the controller, processing the results in parallel, and outputting the results in parallel.