Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co LtdfiledCriticalNippon Electric Co Ltd
Priority to JP7684278ApriorityCriticalpatent/JPS553093A/ja
Publication of JPS553093ApublicationCriticalpatent/JPS553093A/ja
Publication of JPS6131897B2publicationCriticalpatent/JPS6131897B2/ja
System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices