JPS6131897B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an emulator (integrated circuit for computer development, hereinafter referred to as evachip) used when developing a system using a computer.

Recently, one-chip microcomputers that contain ROM, RAM, and CPU on one chip have begun to be used in many industrial fields, but because the application fields are diverse, one-chip microcomputers have the same architecture and different types of instructions. Usually, several types of products are prepared depending on the size of the memory, the size of the memory capacity, etc. The EV chip has all the command functions of these several types of microcomputers, and when a system is developed using a specific microcomputer, it is used as a substitute for that microcomputer. Therefore, considering economic efficiency, versatility, compatibility, etc., it is made to fit the microcomputer with the greatest functionality.

From this, Aeser, which uses microcomputers to develop systems with functions tailored to the application, understands the architecture that has the same command chain, from large systems to small systems, depending on the application, using a single evachip. if,
It has become possible to develop systems using various microcomputers.

Here, instructions for a higher-level machine that have a variety of functionally different instruction functions include instructions for a lower-level machine that has fewer instruction functions (this is said to be a subset of instructions) for a single chip of the same architecture. Let's take the case of a series of microcomputer products as an example.

Now, the command subset relationship between the A, B, C, and D microcomputer series products and the microcomputer eva chip E is E=A>
Suppose that B>C>D. In other words, the microcomputer A includes the instructions of the microcomputers B, C, and D, the microcomputer B includes the instructions of the microcomputers C and D, and the microcomputer C includes the instructions of the microcomputer D. It includes instructions, and these A,
E, which is an advanced chip of the B, C, and D microcomputer series products, indicates that it is the highest model, that is, the number of instructions and functions are equivalent to that of A, which has the largest number of instructions.

Here, a user who is trying to develop a system using the microcomputer B using Evachip E may mistakenly program the program with instructions that microcomputer A has that microcomputer B does not have. In this case, since Evachip E has all the instruction functions of A's microcomputer, a microcomputer system is manufactured according to a program that uses the instructions of A's microcomputer, and it becomes a product as an integrated circuit. When it was completed, it was discovered that the system that had been developed for the first time did not work with the command functions of B's microcomputer, resulting in a large amount of manufacturing costs and wasted time in redevelopment.

When the present invention is used as a microcomputer evachip for a lower model of a 1-chip microcomputer series product that has the instruction function of a higher-order model, the system can be programmed normally using only the instruction function of the lower-order model. The purpose of this invention is to provide an integrated circuit for computer development that is guaranteed to operate as expected.

The integrated circuit for developing a microcomputer of the present invention has a selection circuit that can select various functions of the microcomputer or, in the case of a multi-chip type, in addition to some of the various functions, an instruction function according to each model. be.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

Figure 1 shows an embodiment of the integrated circuit for developing microcomputers according to the present invention.
The subset relationship of instructions held by microcomputers A, B, C, and D is E=A>B>C>D. T indicates a test terminal, which is used to test the eva-chip and is normally connected to the "0" level. A, B,
C is the input port, and the signal line IP is the input port I
It is used as a signal line for inputting external signals (e.g., input signals from a keyboard, etc.) to specified registers, buffers, etc. within the EV chip through _A , I _B , and I _C , and is connected to a designated circuit within the EV chip. . On the other hand, input ports I _A , I _B , and I _C are connected to respective input terminals of AND gates G _A , G _B , and _GC ,
A test terminal T is connected to the other input terminal of each of the AND gates G _A , G _B , and G _C . Furthermore, AND gate G _A is connected to flip-flop F _A and OR gates O _B and O _C , which are in turn connected to AND gates G _B and C _C , and AND gate G _C is connected to OR gate O _C. OR gates O _B and O _C are connected to corresponding flip-flops F _B and F _C , respectively, and flip-flops F _A and F _B are reset by a system reset signal R. The outputs of these flip-flops F _A , F _B , and F _C are connected to an instruction decoder ID as shown below.

- F _C is connected to the instruction decoder gate DC of an instruction group that is not in the microcomputer D but is in the microcomputer C.

- F _B is connected to an instruction decoder gate DB of an instruction group that is not in microcomputer C but is in microcomputer B.

- F _A is connected to an instruction decoder gate DA of an instruction group that is not present in microcomputer B but is present in microcomputer A.

The setting conditions for these flip-flops F _A , F _B , and F _C are as follows. That is, when a signal is input from the test terminal T and the input port I _A , the flip-flops F _A , F _B , F _C have the following signals.
When signals are input and set through AND gates G _A and OR gates O _B and O _C , and similarly, when test terminal T and input port I _B are input, flip-flops F _B and F _C are set, and test terminal T is input. When a signal is input from input port I _C , only flip-flop F _C is set.

Here, when the system reset signal R is input and the system starts operating, only the instructions of the lowest model microcomputer D (instruction group indicated by DD of the instruction decoder) are working, but if necessary, For example, if you want to use microcomputer B, apply input signals to test terminal T and input port _IB , set flip-flops F _B and F _C , and the DB, DC, and DD portions of the instruction decoder ID will be Since it is in the active state, this Evachip E functions equivalently to the microcomputer B.

In this way, in this embodiment, the instruction decoder is divided into four blocks (DA,
DB, DC, DD) and has a selection circuit that selects the block with the desired instruction function, so the test terminal T and input ports _IA , _IB , I
By operating C and _C appropriately, the same instructions as those of the microcomputer to be used can be transmitted to the E chip.
can be made operational. Therefore, the system will not be developed with incorrect command functions, and the time and effort required for redevelopment can be eliminated.

FIG. 2 shows another embodiment of the invention.

In this embodiment, the outputs of flip-flops F _A ', _B ', F _C ' are connected to corresponding blocks D _A ', D _B ', D _C ' of an instruction decoder ID'.
Each block D _A ', D _B ', D _C ', and D _D ' has the same function as the blocks DA, DB, DC, and DD in FIG. Signal lines S _A , S _B , and S _C for inputting instructions to set the flip-flops are input to the set input terminals of the flip-flops F _A ′, F _B ′, and FC _′ , respectively. _A ′, F _B ′, F
_C ' is set by the set signal R' and becomes an initial state.

The signals input from the signal lines S _A , S _B , and S _C to the flip-flops F _A ′, F _B ′, and _FC ′ are signals decoded by the decoder block DD ′ of the instruction decoder ID. Yes, decoder block
DD' only needs to contain instructions for specifying each flip-flop. In this case, flip-flops F _A , F _B , and F _C are all set by the system set signal R, but flip-flops can be freely set by a command.
It is possible to set flops F _A , F _B , and F _C .

According to the embodiment shown in FIG. 2, if a decoder block having the instruction function to be used is incorporated into a program in advance, the decoder block DD' to each flip-flop F is programmed in accordance with the program.
The signals that select _A ′, F _B ′, and _FC ′ are connected to signal lines S _A and S
It is input to each flip-flop through _B and _SC , and a necessary decoder block is selected, without driving a decoder block that has an instruction function not found in the microcomputer actually used. Therefore, when developing a system using Evachip E, the system can be reliably developed using the instruction function of the microcomputer actually used.

Furthermore, the present invention is not limited to these embodiments, but may be any device that divides the instruction decoder in the everchip into blocks according to the instruction model and has selection means for selecting this unit block. Logic circuits that combine gates can be connected to other logic gates (NAND gates,
A NOR gate etc. may also be used.

Further, each instruction decoder may be selected by not only disabling the instruction decoder but also opening and closing a gate at its input section.

In addition, in the configuration of flip-flops F _A , F _B , F _C , the output of flip-flop F _A is input to the decoder block DA and also to the set input terminals of flip-flops F _B and F _C . The output of the flip-flop F _B is input to the decoder block DB, and the flip-flop
It may be connected to the set input terminal of the flop _FC , and so-called flip-flops may be connected in series with each output line.

Furthermore, the subset relationship of instructions held by each microcomputer in the microcomputer series for which systems are designed using the EVAchip is not limited to the above-mentioned instructions for higher-level models that include instructions for lower-level models, but also for other relationships. In short, if all the instructions of the microcomputer series are provided in the evachip and the instructions can be selected as appropriate, the same operation as in the above embodiment is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing yet another embodiment. ID, ID′...Instruction decoder,
DA, DB, DC, DD, DA′, DB′, DC′, DD′...
Decoder block, F _A , F _B , F _C , F _A ', F _B
′, F _C ′……Flip-flop, O _B , O _C ……
OR gate, G _A , G _B , G _C ...AND gate, T
...Test terminal, I _A , I _B , I _C ... Input port, I _P ... Signal line, S _A , S _B , _SC ... Set input signal line, R, R' ... Reset input signal line .

Claims (1)

[Claims] 1 An integrated circuit for computer development for a plurality of microcomputers configured with the same architecture, which includes a common instruction decoder commonly used by all of the plurality of microcomputers, and a common instruction decoder used only for the first microcomputer. a first instruction decoder used only for the first and second microcomputers; the common instruction decoder is accessible at all times; 1. An integrated circuit for computer development, characterized in that said second instruction decoder is selected so as to be accessible only to said first and second microcomputers.