JPS6130778A - Test circuit - Google Patents

Abstract

PURPOSE:To hold back power consumption in a test circuit, by having one of a plurality of resistances composed of a MOS transistor in which a gate electrode is controlled by a standby signal outputted from a CPU to cut off the flow of current from a test terminal. CONSTITUTION:A test circuit 20 of a microcomputer 10 is made up of an input terminal (e), an inverter (k), a NAND gate (i), a resistance R3 and a MOS transistor (g). Then, the resistance ratio is set for a specified value between the resistance R3 and the resistance between the source and drain of the MOS transistor (g) conducting. When the demand for the standby state is generated, a CPU30 puts the computer 10 to the standby state while bringing a standby signal (f) to a low level to turn OFF the MOS transistor (g) causing the current to be shut down as flowing to the GND from the input terminal (e) thereby suppressing holding back power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a microcomputer test circuit that is configured in one step and has a standby function.

[Prior art]

Internal R
It is generally considered impossible to check the operation of the OM because the contents of the internal ROM differ from user to user.

Therefore, a test circuit and an input terminal (test terminal) for a test circuit control signal are provided inside the chip, and the following microcomputer tests are performed while controlling the test circuit using the control signal. First, outside the chip: input the instruction code data from the outside using an external ROM (memory of an automatic measuring device, etc. for measuring the IC) for two-pronged C-star testing, and check the operation of everything other than the internal ROM. .

Next (=The internal ROM outputs its own ROM code data to the external terminal, and the contents of the internal ROM are tested. However, such a test terminal is completely unnecessary in normal operating conditions. Therefore, an independent test terminal without providing
A test circuit is used in which a specific input terminal is shared with a test terminal and a high-voltage control signal that is not possible in a normal operating state is input to this terminal (thus, the test state is established).

Figure 2 is a block diagram of the main parts of a microcomputer that incorporates a conventional example of such a test circuit. Microcomputer 1 includes test circuit 2, CPU 5, and internal ROM
4 and a bus 5, to which an external ROM 6 is provided. The test circuit 2 includes a test terminal C, an inverter a,
b. It consists of a resistor R1°R. Here, the resistance ratio of the resistors R+ and Rmaro is determined depending on the voltage level Va applied to the test terminal C by the output levels va and vb of the inverters a and b, depending on the three types of modes M+ to M shown in Table 1.
1 = predetermined to be 3.

However, in Table 1, H is the power supply potential, L is the ground potential,
HV indicates a specific potential higher than the power supply potential. In mode NLI, the user operates the microcomputer 1 internally.
This is the state when using the M4. At this time, the CPU 6 outputs the control signal 7 to the internal ROM 4 and operates according to the contents of the internal ROM 4. Mode Mm is the state when the microcomputer 1 is used with the external ROM 6,
The CPU 3 outputs the control signal 8 to the external ROM 6, and outputs the control signal 8 to the external ROM 6.
It operates according to the contents of OM6. Mode M3 is a test state, in which code information, which is the content of internal ROM 4, is output to the outside via path 5 in response to control signal 7.

However, in this microcomputer 1, a request to enter the standby state occurs in the CPU 6 while it is being used in mode M1.
Even if microcomputer 1 enters standby mode,
Since the current continues to flow from the test terminal C to the resistor R1°R1 and then to GND, there is a drawback that low power consumption during standby cannot be achieved.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a test circuit that can suppress current consumption in a standby state and reduce power consumption of a microcomputer.

[Structure of the invention]

The test circuit of the present invention has a plurality of resistors connected in series between an input terminal and a reference potential, and in which the connection point of each resistor is an output terminal, at least one of the plurality of resistors is It is characterized by being composed of a MOS transistor whose gate electrode is controlled by a standby signal output from the CPU.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer having a test circuit according to an embodiment of the present invention.

The microcomputer 10 has a test circuit 20, Cpty
30. Internal ROM4Q for programming, external ROM60 for testing. CPU, 30 and internal ROM 40 and external RO
There are 50 paths connecting M6Q.

Internal ROM40. The contents of the external ROM 60 are transferred from the CPU 60 to the internal ROM 40. The control signals 70 and 80 output to the external ROM/;)Q are output to the bus 50.

The test circuit 20 consists of an input terminal e, an inverter h, a Nandt gate 11 resistor Rs, and a MOS transistor g.

The resistance ratio between the resistance Rm and the resistance between the source and drain of the MOS resistor g when conductive is determined by the output level Vh of the inverter h and the Nandt gate 1 depending on the voltage level V applied to the input terminal e.

Vl is set in advance so that the modes M1 to Mml in Table 2 are satisfied.

Table-2 However, the modes of Table-2 are Ms ~ Ms, H, L,
HVs are shown with the same symbol in Table 1. Note that the standby signal f, which is low level when a request to enter the standby state is generated in the CPU 30 and high level when no standby request is generated, is transmitted to the CPU 6.
0 to test circuit 201=output.

Next::The operation of this embodiment will be explained. If a standby request has not occurred, the standby signal f is at a high level, so the MOS transistor g is in the on state, and each of the modes Ml to Ms shown in Table 2 is activated according to the voltage level V of the input terminal e. state. Next (=, When a request to enter the standby state occurs, the cpu 30 puts the microcomputer 10 into the standby state, and also sets the standby signal f to low level to the MOS transistor g.
is turned off, cutting off the current flowing from input terminal C to GND.

By the way, even in the standby state, if the voltage level V of input terminal e is high level, the outputs Vh and V4 of inverter h and Nant gate 5 are low level, respectively.
If the voltage level V of the input terminal e is at a low level, the outputs of the inverter h and the NAND gate are both at a high level and mode MS is maintained, so mode M2 is maintained. , as soon as the standby state is released) second mode M1. M
s can be performed.

〔Effect of the invention〕

As explained above, the present invention can prevent current from flowing from the test terminals of the test circuit in the standby state (secondary state), thereby providing a test circuit with reduced power consumption. Low power consumption is achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of a microcomputer incorporating a test circuit according to an embodiment of the present invention (2), and FIG. 2 is a block diagram of main parts of a microcomputer incorporating a conventional test circuit. i, io ...Microcomputer 2.20...Test circuit 3.60...CPU 4.40...Internal ROM 5.50...Path 6160...External ROM 7.8, 70.80...・Control signals c, e... Test terminals a, b, h... Inverter f... Standby signal g... MOS transistor i... Nant gate Rs, Rt, Rs... Resistor. Patent application People NEC Corporation Figure 1 5P+2

Claims (1)

[Claims] In a microcomputer test circuit having a plurality of resistors connected in series between an input terminal and a reference potential, and in which the connection point of each resistor is an output terminal, at least one of the plurality of resistors is connected to the CPU. A test circuit comprising a MOS transistor whose gate electrode is controlled by an output standby signal.