JPS5884330A - Input circuit of microprocessor - Google Patents

Abstract

PURPOSE:To minimize the power consumption regardless of the ON/OFF of a switch, etc. of an input circuit, by pulling up or down an input terminal only in a period of the executing cycle of a microprocessor. CONSTITUTION:A switch pull-up controlling circuit 6 receives the signal of a control circuit 7 of a microprocessor and applies the signal to pull up an input terminal 10. The output signal of a buffer 8 is set at a high level only when the waveform of the switch pull-up is set at a high level. Thus the terminal 10 is pulled up via a current limiting resistance 9. In this case, the signal of a high level and the signal of a low level are fed to an inverter 4 when a switch 1 is opened and closed, respectively. A switch input circuit 5 decides a high or low level. The output signal of the buffer 8 is always set at a low level when no switch sense instruction is given. Thus no electric power is consumed regardless of the state of the switch 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit, particularly an input circuit that is optimal for various low power consumption systems using a microprocessor made of i-MOS or the like.

``Conventionally, there was an input circuit as shown in FIG. 1. In other words, by opening and closing / with a switch, 1 high" or °low" level can be input. It is applied to the input terminal IO of the circuit. Switch input circuit via O-MOS inverter tag! is configured to be input. However, in the case of a circuit with such a configuration, the input circuit must definitely receive a "high" or "low" level! In order to input the resistor J' (MOS
A pull-up (or pull-down depending on the circuit) is required. Therefore, the switch / is always
If the switch is open, no power is consumed; however, if the switch is always closed, current always flows, consuming power. When a large number of such switches exist, there is a drawback that a large amount of power is consumed. In order to overcome this drawback, there is a circuit shown in FIG. By configuring the switch like a 3-terminal transfer switch λ and using transfer switch 2 to switch between the power supply and ground, a circuit that does not have any power consumption problems can be configured, but only 3 terminals are required as a switch. Moreover, since the power supply and ground are located close to each other, a design that takes into account moisture resistance, etc., is required to prevent short circuits.

The present invention has been made in view of the above points and in order to eliminate the above drawbacks, and only when an instruction to input information from an input terminal of a microprocessor or the like is executed, the input terminal is pulled up or pulled down. The purpose is to provide input circuits for microprocessors, etc.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a circuit diagram of one embodiment of the input circuit of the microprocessor of the present invention. / is a switch, and by opening and closing it, the 1 high or low level is output to the rc input terminal 1.
Give to 0. 2 is MicroProcera t(7)Fnjo-
Le circuit,! is a switch pull-up control circuit. The switch pull-up control circuit provides a signal to pull up the input terminal /θ. l is a buffer, ri is a current limiting resistor, and from the 0 input terminal 10 connected to the input terminal /θ, a switch input circuit is connected as an input circuit via a C-MOS inverter tag! The output is input to the microprocessor control circuit 2, which is configured to open the gate of the input circuit upon receiving a signal from the switch pull-up control circuit 2, etc. (not shown here). . The circuit shown in FIG. 3 shows the configuration of only the /input terminal.

FIG. 9 shows a time chart when the microprocessor executes the switch sense command. To simplify the explanation, it is assumed that the microprocessor/machine cycle takes up y main clock cycles, as shown in Figure 9, of which 2 clocks are used to fetch instructions, and the remaining cycles Assume a microprocessor where minutes is the execution time of the instruction.

When the switch command is executed, only when the switch pull-up waveform is at a high level as shown in FIG. 9, if the output signal from the buffer in FIG. The input terminal /θ is pulled up through the inverter tag, and when the switch / is open, a "high" level signal is input to the inverter tag, and when the switch / is closed, a "low" level signal is input to the inverter tag. These signals enable the switch input circuit to reliably determine whether the level is high or low.When the switch sense command is not executed, the output signal from the buffer is always at a "low" level. Power is not dissipated whether the switch / is open or closed. If the switch / is connected to the power supply instead of being connected to ground, it is a pull-down instead of a pull-up. Needless to say, it is necessary.

Figure 5 shows only the main parts of the circuit in Figure 3 as a concrete G-MO8.
FIG. 3 is a circuit diagram showing an example in which the circuit diagram of ICi is replaced. /2 is a HAND gate, which accepts the address as input.
Upon receiving the enable signal AE and the read enable signal RE, a pull-up signal is applied to the input terminal 10 via an inverter 5// and a current limiting resistor. In addition, a switch for opening and closing the ground is connected to the input terminal 10, and the other side is input to a C-MOS inverter via a (!-MOS inverter tag. What is a C-MOS inverter? P channel yos/! and N channel Mo
◎P channel M O8/j consisting of s/l
P-channel Mas/41 is connected to NF-Yannel uos/g, and N-channel MO8/7 is connected to NF-Yannel uos/g. The output of NAND gate/2 is P channel MO
It is applied to the gate of MO 8/ and to the gate of N-channel MO 8/7 via inverter /3. Therefore, a gate circuit is constituted by the P-channel MO 8/4, the inverter /3, and the N-channel MO 8/2. C-MO
S inverter/! The output of is given to data bus line DB. vDD connected to Pf-Jannel MO8/g is a power supply. Now read enable signal RE
If the address group enable signal AE is input to the NAND gate/2 at a "high" level, its output will be "
Low level, 10-1 level at the gate of P channel was/'l, N channel MOS/7
A "high" level is input to the gate of , the source and drain of both MO3 become conductive, and the C-MOS inverter /! A power supply vDD is connected to. Inverter/
Since the output of / becomes 'high' level, it becomes a signal that pulls up the input terminal /θ.If switch / is open, a signal of 'high' level is given to the inverter tag, and its The output becomes "a low" level and becomes C again.
Since it is inverted by the -MOS inverter /, a "high" level is output and is applied to the data bus line DB.

When the read enable signal RR and the address enable signal AH are not input to the NAND gate/2 at the same time, the output of the NAND gate/2 becomes a "high level", and therefore the output of the inverter// becomes a "low" level. Therefore, the input terminal /θ becomes “low” level, and
Power is not consumed regardless of whether the switch is open or closed. At this time, P channel MOS/& and N channel MO8/7
becomes non-conductive.

With this configuration and operation of the present invention, the input terminal is pulled up (or pulled down) only for a moment during the execution cycle of the microprocessor, so that the open/close state of switches, etc. connected to the input terminal of the input circuit can be changed. It has the effect of minimizing power consumption regardless of the situation, and is suitable for systems driven by batteries, C1-MOS, etc.
For an input circuit of

[Brief explanation of the drawing]

1 and 2 are circuit diagrams according to the conventional example, FIG. 3 is a circuit diagram according to the present invention, FIG. 9 is a diagram showing a time chart of the circuit in FIG. 3, and FIG. It is a circuit diagram embodying the main part of □ in more detail. /;Switching;C-MOS inverter! ;Switch input circuit B ;Switch pull-up control circuit 7;Microprocessor control circuit, etc.;Buffer;Current limiting resistor/θ;Input terminal

Claims (1)

[Claims] An input circuit for a microprocessor, characterized in that the input terminal is pulled up or pulled down only when an instruction to input information from the input terminal of the microprocessor is executed.