JPS6130048A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6130048A
JPS6130048A JP59151413A JP15141384A JPS6130048A JP S6130048 A JPS6130048 A JP S6130048A JP 59151413 A JP59151413 A JP 59151413A JP 15141384 A JP15141384 A JP 15141384A JP S6130048 A JPS6130048 A JP S6130048A
Authority
JP
Japan
Prior art keywords
island
films
separating
grid
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59151413A
Other languages
Japanese (ja)
Inventor
Hiroyasu Uehara
上原　啓靖
Tokuo Nakamura
徳雄 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59151413A priority Critical patent/JPS6130048A/en
Publication of JPS6130048A publication Critical patent/JPS6130048A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To conduct buffer effection of chipping by a method wherein a separating island, on which a circuit element is not mounted, is formed between a die section and a separating island for grid, and spreading over the said island and the separating island for the grid, an oxide film and a passivation film are formed, isolating from the same films on the die section. CONSTITUTION:Separating islands 8, 8', which a circuit element is not mounted on, is formed between die sections 1, 1' and a separating island 3 for a grid on a poly-Si layer 5, and a passivation film 9, 9' and an oxide film 10, 10' are formed spreading over thereon. However, these films are formed isolating from passivation films 6, 6' and oxide films 7, 7' which are formed extending horizontally and partially on the die sections 1, 1' onto the separating islands 8, 8'. When a grid 2 of a dielectric separating Si substrate by this constitution is cut by a blade, chipping is stopped at near by a contact point of the oxide films 10, 10' and an oxide film 4, and the oxide films 7, 7' and the passivation films 6, 6' are not injured. This constitution enable cutting speed and exchanging period of the blade to be normal even through the grid 2 is narrow, furthermore, to prevent injury surely.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は半導体装置、特に誘電体分離シリコン基板に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a dielectrically isolated silicon substrate.

（従来の技術） 従来の誘電体分離シリコン基板のグリッドライン部分の
断面図を第２図に示す。この図において、１　、　Ｉ’
ｌｌ；ｒダイス部、２はダイス部ｌ、１′相互間のグリ
ッドライン、３はグリッドライン用分離島、４け分離島
酸化膜、５はポリシリコン層、６，６′はダイス部り、
１′上の／母ツシベーショシ膜、７゜７′ハ同ダイス部
１，１′上の酸化膜である。(Prior Art) A cross-sectional view of a grid line portion of a conventional dielectrically isolated silicon substrate is shown in FIG. In this figure, 1, I'
ll;r dice part, 2 is the dice part l, 1' is a grid line between each other, 3 is an isolation island for grid lines, 4 is an isolation island oxide film, 5 is a polysilicon layer, 6 and 6' are die parts,
7.7' is the oxide film on the die portions 1 and 1'.

このような誘電体分離シリコン基板において、グリッド
ライン２をダイシングブレードにて切断すると、ブレー
ドは、グリッドライン用分離島３→分離島酸化膜４→、
ＪＰＩＪシリコンｆ＃Ｉ５を順次通過する。In such a dielectric isolation silicon substrate, when the grid line 2 is cut with a dicing blade, the blade separates the grid line isolation island 3→isolation island oxide film 4→,
Sequentially passed through JPIJ silicon f#I5.

ところで、誘電体分離シリコン基板のグリッドラインは
、スクライプ（切断）の際のチッピングの発生によるダ
イス不良率を減少させるため、誘電体分離でない通常の
シリコン基板のグリッドラインよりも幅を広くする必要
があった。By the way, the grid lines of a dielectric-separated silicon substrate need to be wider than the grid lines of a regular silicon substrate that is not dielectric-separated in order to reduce the die defect rate due to chipping during scribing (cutting). there were.

（発明が解決しようとする問題点） しかるに１通常のシリコン基板のグリッドライン幅８０
Ｉｔｍ程度に対してグリッドライン幅を１２０〜１６０
μ露程度に広くしても、従来の誘電体分離シリコン基板
ではチッピングが起シ、ダイス歩留りが大幅に低下した
。すなわち、分離島酸化膜４＃−Ｘ厚さ１μｍ程度の熱
酸化膜であル、スクライブに際してはブレードがその酸
化膜４によって目づまシを起す。これによシ、ブレード
が不均一に厚くなシ、かつグリッドライン２の広範囲の
部分を切断することになシ、その結果グリッドライン用
分離島３にクラックなどのダメージを与え、ついにはダ
イス部り、１′上のパッシベーション膜６．６′および
酸化膜７　、７’ｆｆ、破壊、いわゆるチッピングが起
シ、ダイス歩留シを大幅に低下させる。(Problem to be solved by the invention) However, 1. The grid line width of a normal silicon substrate is 80 mm.
Grid line width is 120-160 for Itm
Even if the thickness is as wide as μ, chipping occurs in conventional dielectric-separated silicon substrates, resulting in a significant drop in die yield. That is, since the isolated island oxide film 4#-X is a thermal oxide film with a thickness of about 1 μm, the blade is clogged by the oxide film 4 during scribing. As a result, the blade is unevenly thick and cannot cut a wide area of the grid line 2, which results in damage such as cracks to the grid line separation island 3, and finally the die part. As a result, the passivation films 6, 6' and oxide films 7, 7'ff on 1' are destroyed, so-called chipping, which significantly reduces the die yield.

そこで、ダイシングのスピードを従来の暑。以下にし、
ブレードのドレッシングもシリコン基板１枚毎に行って
、チッピングの発生を減少させることが考えられる。し
かるに、この方法は、量産性に欠け、実用的でない。Therefore, the speed of dicing was changed to conventional heat. below,
It is possible to reduce the occurrence of chipping by dressing the blade for each silicon substrate. However, this method lacks mass productivity and is not practical.

また、前述のようにクリットライン幅を広くすルト、シ
リコン基板におけるグリッドライン面積が増大し、搭載
可能なダイス数が減少するという欠点がある。Furthermore, as described above, when the width of the crit line is widened, the grid line area on the silicon substrate increases and the number of mountable dice decreases.

（問題点を解決するための手段） そこで、この発明では、ダイス部とグリッドライン用分
離島との間に、回路素子を搭載しない分離島を設け、か
つこの回路素子を搭載しない分離島′とグリッドライン
用分離島の上部に跨がって酸化膜とパッシベーション膜
とを、前記ダイス部上の酸化膜およびノ？ツシベーショ
ン膜と離して設ける０ （作用） このようにすれば、回路素子を搭載しない分離島と、そ
の分離島およびグリッドライン用分離島の上部に跨がっ
て設けた酸化膜およびパッシベーション膜とがチッピン
グ緩衝作用をする。(Means for solving the problem) Therefore, in the present invention, an isolation island on which no circuit element is mounted is provided between the die part and the grid line isolation island, and an isolation island 'on which no circuit element is mounted is provided. An oxide film and a passivation film are placed over the top of the isolation island for the grid line, and an oxide film and a passivation film are formed on the die part and the top of the grid line isolation island. Provided separately from the passivation film 0 (Function) In this way, the isolation island on which no circuit element is mounted, and the oxide film and passivation film provided over the isolation island and the grid line isolation island. acts as a chipping buffer.

（実施例） 第１図はこの発明の一実施例を示す誘電体分離シリコン
基板のグリッドライン部分の断面図である。この図にお
いて、１　、　ＩＴＪ従来と同様にダイス部、２はダイ
ス部１，１′相互間のグリッドライン、３はグリッドラ
イン用分離島、４は分離島酸化膜、５に支持体としての
ポリシリコン層であるが、この一実施例では、ダイス部
１，１′とグリッドライン用分離島３との間に、回路素
子を搭載しない分離島８．８′が設けられる。また、こ
の回路素子を搭載しない分離島８，８′とグリッドライ
ン用分離島３の上部に跨がってパッシベーション膜９．
９′および酸化膜１０　、１０’が設けられる。その場
合、パッシベーション膜９，９′および酸化膜１０　、
１０’に、分離島８．８′上に一部延在して設けられる
ダイス部り、１′上のｉＪ？ツシベーション膜６．６′
および酸化膜７，７′と接しないように設けられる。(Embodiment) FIG. 1 is a sectional view of a grid line portion of a dielectrically isolated silicon substrate showing an embodiment of the present invention. In this figure, 1 is the die part as in the conventional ITJ, 2 is the grid line between the die parts 1 and 1', 3 is the isolation island for the grid line, 4 is the isolation island oxide film, and 5 is the polyester as a support. Although the silicon layer is a silicon layer, in this embodiment, an isolation island 8.8' on which no circuit element is mounted is provided between the dice portions 1, 1' and the grid line isolation island 3. Furthermore, a passivation film 9 is formed over the isolation islands 8 and 8' on which no circuit elements are mounted and the upper part of the grid line isolation island 3.
9' and oxide films 10 and 10' are provided. In that case, the passivation films 9, 9' and the oxide film 10,
At 10', there is a die part extending partially over the separation island 8.8', and at iJ? Tsusivation film 6.6'
and are provided so as not to be in contact with the oxide films 7, 7'.

このように構成された誘電体分離シリコン基板のグリッ
ドライン２全ダイシングプレートで切断すると、第１図
で説明したのと同じ理由でグリッドライン２とパッシベ
ーション［９，９’およヒ酸化膜］　０　、１０’にお
いてチッピングが起るが、酸化膜］　０　、１０’と分
離島酸化膜４との接点部付近でチッピングが停止するた
め、ダイス部り、１′上のパッシベーション膜６，６′
および酸化膜７，７′に対しては損傷を与えることにな
い。すなわち、分子ｌｔｍ　ｓ　＋　８／、　／４’ツ
シベーション膜９．９′および酸化膜１０　、１０’が
チッピング緩衝作用をする。When the entire grid line 2 of the dielectric-isolated silicon substrate configured in this way is cut by the dicing plate, the grid line 2 and passivation [9, 9' and arsenic oxide film] 0 for the same reason as explained in FIG. 1. , 10', but the chipping stops near the contact area between the oxide film] 0, 10' and the isolation island oxide film 4.
Also, there is no damage to the oxide films 7, 7'. That is, the molecules ltm s + 8/, /4', the oxidation films 9 and 9' and the oxide films 10 and 10' act as a chipping buffer.

この作用による前記損傷防止効果は、グリッドライン２
の幅が、誘電体分離でない通常のシリコン基板のグリッ
ドライン幅と同様に狭い場合であっても充分に発揮され
る。しかも、ダイシングのスピードを通常のスピードに
設定し、かつ通常の場合と同じブレードの交換周期でス
クライプした場合でも、損傷を確実に防止できるのであ
る。The above-mentioned damage prevention effect due to this action is due to the fact that the grid line 2
Even when the width of the grid line is as narrow as the grid line width of an ordinary silicon substrate without dielectric isolation, the effect can be sufficiently exhibited. Furthermore, damage can be reliably prevented even when the dicing speed is set to the normal speed and the scribing is performed at the same blade replacement frequency as normal.

第３図は、上記−実施における各部の好ましい数値の一
例を示す図である。酸化膜１０　、１０’の１１１１３
６μｍ１パツシベーシヨン膜９，９′の幅に４しｌ１回
路素子を搭載しない分離島８，８′の幅Ｖｓ４０μｍ、
グリッドライン用分離島３（グリッドライン２）の幅は
８０μｍ１分離島酸化膜４が酸化膜１０　、１０’に接
する部分の幅は２０μｍ。FIG. 3 is a diagram showing an example of preferable numerical values of each part in the above-mentioned implementation. 11113 of oxide film 10, 10'
The width of the isolation islands 8, 8' on which no circuit elements are mounted is 40 μm, and the width of the isolation islands 8, 8' is 40 μm.
The width of the grid line isolation island 3 (grid line 2) is 80 μm, and the width of the portion where the isolation island oxide film 4 contacts the oxide films 10 and 10' is 20 μm.

分離島８，８′の深さは２０μｍとするのが好ましい。The depth of the isolation islands 8, 8' is preferably 20 μm.

また、酸化膜１０　、１０’は０．１μｍ厚程鹿の熱ｔ
、長ｒＲ化８、Ａ’ツシベーション膜９．９’は１μｍ
厚程鹿のＣＶＤによるリンガラス膜からなる。In addition, the oxide films 10 and 10' have a thickness of 0.1 μm due to the deer's heat temperature.
, long rR 8, A' tsivation film 9.9' is 1 μm
It consists of a phosphor glass film made by CVD of Atsushi Shika.

（発明の効果） 以上詳述したように、この発明の半導体装置に、ダイス
部とグリッドライン用分離島との間に、回路素子を搭載
しない分離島を設け、かつこの回路素子を搭載しない分
離島とグリッドライン用分離島の上部に跨がって酸化膜
とノぐツシベーション膜とを、前記ダイス部上の酸化膜
およびパッシベーション膜と離して設けるようにしたの
で、グリッドライン幅を狭くして、スクライプの際の、
ダイス部上ノパツシベーション膜および酸化膜の損傷を
防止できる。しかも、ダイシングのスピードを通常のス
ピードに設定し、かつ通常の場合と同じブレードの交換
周期でスクライプして、前記損傷を確実に防止できる。(Effects of the Invention) As detailed above, in the semiconductor device of the present invention, an isolation island on which no circuit element is mounted is provided between the dice portion and the grid line isolation island, and a part on which this circuit element is not mounted is provided. Since the oxide film and passivation film are provided over the remote island and the upper part of the grid line separation island, and are separated from the oxide film and passivation film on the die part, the grid line width can be narrowed. So, when scriping,
Damage to the passivation film and oxide film on the die portion can be prevented. Moreover, the damage can be reliably prevented by setting the dicing speed to a normal speed and scribing at the same blade replacement frequency as in normal cases.

したがって、ダイス歩留シが大幅に向上するとともに、
グリッドライン面積の削減に伴い一基板機りの搭載可能
なダイス数を増大させることができ、加えて量産性を高
めることができる。Therefore, the die yield is greatly improved, and
As the grid line area is reduced, the number of dies that can be mounted on a single substrate machine can be increased, and in addition, mass productivity can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の半導体装置の一実施例を示す断面図
、第２図は従来例を示す断面図、第３図は上記一実施例
における各部の好ましい数値の−Ｊ、１′・・・ダイス
部、３・・・グリッドライン用分離１６　、６’・・・
パッシベーションａ、７　、７’・・・酸化膜、　８　
、８’・・・分離Ｌ　９　、９’・・すｆツシペーショ
ン膜、１０　、１０’・・・酸化膜。FIG. 1 is a cross-sectional view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is a cross-sectional view showing a conventional example, and FIG.・Dice part, 3... Grid line separation 16, 6'...
Passivation a, 7, 7'... oxide film, 8
, 8'... Separation L 9 , 9'... Suffipation film, 10, 10'... Oxide film.

Claims (1)

【特許請求の範囲】[Claims] 　誘電体分離シリコン基板において、ダイス部とグリッ
ドライン用分離島との間に、回路素子を搭載しない分離
島を設け、かつこの回路素子を搭載しない分離島とグリ
ッドライン用分離島の上部に跨がつて酸化膜とパツシベ
ーシヨン膜とを、前記ダイス部上の酸化膜およびパツシ
ベーシヨン膜と離して設けたことを特徴とする半導体装
置。In the dielectric isolation silicon substrate, an isolation island on which no circuit elements are mounted is provided between the die part and the isolation island for grid lines, and the isolation island on which no circuit elements are mounted and the upper part of the isolation island for grid lines are provided. A semiconductor device characterized in that an oxide film and a passivation film are provided separately from the oxide film and passivation film on the die portion.
JP59151413A 1984-07-23 1984-07-23 Semiconductor device Pending JPS6130048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59151413A JPS6130048A (en) 1984-07-23 1984-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59151413A JPS6130048A (en) 1984-07-23 1984-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6130048A true JPS6130048A (en) 1986-02-12

Family

ID=15518060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59151413A Pending JPS6130048A (en) 1984-07-23 1984-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6130048A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919713A (en) * 1994-01-28 1999-07-06 Fujitsu Limited Semiconductor device and method of making

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919713A (en) * 1994-01-28 1999-07-06 Fujitsu Limited Semiconductor device and method of making
US6455945B1 (en) 1994-01-28 2002-09-24 Fujitsu, Limited Semiconductor device having a fragment of a connection part provided on at least one lateral edge for mechanically connecting to adjacent semiconductor chips

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