JPS6129899A - Voice signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an audio signal processing device capable of obtaining an audio signal having a height different from that of an original audio signal.

Prior Art In order to vary the height of an audio signal (herein referred to as an audio frequency signal), conventionally the audio signal is digitized at a predetermined sampling frequency and written to a memory, and the digitized audio signal is It is practiced to read out at a frequency different from the sampling frequency and return it to an analog audio signal with a different height.

This technology is useful when changing the pitch of an orchestral performance recorded on magnetic tape etc. to the singer's preference when using it as accompaniment for singing. This technique is used to eliminate the unnatural feeling of the reproduced sound when playing back a recorded magnetic tape at high or low speed.

First, a conventional audio signal processing device will be described with reference to FIGS. 7 to 9.

FIG. 7 shows an example of the configuration of a conventional audio signal processing device. In this FIG. 7, an audio signal supplied from an input terminal (1) is input to an A/D converter (2) at an appropriate sampling frequency f.
PCM (pulse code modulation) is performed at s (for example, 44.lK11z). This PCM audio signal can be used as a digital memo such as Guinami Soku RAM (January 3).
By the write clock supplied from the write circuit (4) to the write control terminal (3) of the memo 1/3), data is read in word units at a speed corresponding to the sampling frequency as shown in Figure 8. written.

The time Tw required to write N words of data is as follows (
1) It is expressed as follows.

Tw=N/fs...(]) Two readout control terminals (3q) and (3r) of Memo January 3)
) from the readout circuits (5) and (6) to the sampling frequency fs
Read clocks with different frequencies fR are respectively supplied. The data read by the first read circuit (5) is output to one output terminal (30) of the memo i month 3), and the data read by the second read circuit (6) is output to the other output terminal (3p). is output to. The re-output terminals (3o) and (3p) are the fixed contacts (7a) and (
7b), and depending on the connection state of the movable contact (7c), the output terminal (3o) or (3) of the memo 1/3)
The read data is supplied from p) to the D/A converter (8), an analog audio signal having a different height from the original audio signal is reproduced, and is supplied to the output terminal (9).

The ratio between the height of the reproduced audio signal and the height of the original audio signal is expressed by the following equation (2).

K= f R/ f s −+21
That is, when the readout frequency is higher than the sampling frequency, the height of the reproduced audio signal will be higher than that of the original audio signal,
If the readout frequency is lower than the sampling frequency, the height of the reproduced audio signal will be lower than that of the original audio signal.

The value of K is, for example, within the range of 5 to 1/F (half an octave above and below), 'r' = 1.059.
(semitone), and for speech, depending on the tape playback speed, for example 3 to 1/3
is set to

The time TR required to read N words of data at the read frequency fR is expressed by the following equation (3).

TR=N/fR...(3) As is clear from comparing equation (3) and equation (1),
In order to change the height of the reproduced audio signal, if fR: #fs, then T B -1' T 11 is obtained. The time T is the difference between the write time Tw and the read time TR of N words of data.
If d, then from equations (1) to (3)...(4) is obtained.

The amount of data Nd read out at this Td waiting time read frequency fR is expressed by the following equation (5).

Nd = fa - Td = (K1) N...
...(5) This Nd is equal to, that is, f R/ f s >
When it is 1, it is positive, and when fR/fs<1, it is negative, and if a single readout circuit is used, there will be a problem of excess or deficiency of data.

In the device shown in FIG. 7, as described above, two readout circuits (5) and (6) are provided to truncate excess data
Missing data is replenished by repeatedly reproducing the same data.

If K>1, as shown in FIG. 9, the first readout circuit (5) reads the memory (3) having addresses 1 to N indicated by solid lines
At the same time, the second reading circuit (6) starts reading the data written in the first word from the first word.
−1) On the virtual memory shown by the dotted line N words before −
(K-1) Start reading from the Nth word. At this time, since the switch (7) is in the connected state as shown in FIG. 7, the read data output from the memo January 3) is from the first read circuit (5). As is clear from equation (4) above, when time Td has elapsed since both successive readout circuits (5) and (6) started reading, the second readout circuit (6) starts reading the first word. put out. Thereafter, both successive readout circuits (5) and (6) read out the same data in an overlapping manner until the first readout circuit (5) reads the Nth word after a time TR has elapsed from the start of readout. There is. If the connection of the movable contact (7c) of the switch (7) is switched from one fixed contact (7a) to the other fixed contact (7b) within this overramp period, the read data output from Memo January 3) will be The second reading circuit (6) outputs the data reversed by (K-1)N words. When the TR time has passed since the start of reading, the first readout circuit (5) can no longer read data, but the second readout circuit (6) continues to read out data sequentially until the time Tiv has elapsed since the start of readout. When,
Read the Nth word.

As described above, when K>1, missing data is replenished by repeatedly reading data.

The same idea as above can also be applied when K<1. In this case, the time TR for reading N words becomes longer than the write time T11, and the time difference Td between the two wraps around within the read time TR, contrary to what is shown in FIG. The amount of data read at the read frequency fR within the write time Th is f
H-Tw=KN(kN)word(゛) Therefore, in this case, the first readout circuit (5) reads from the first word,
The second reading circuit (6) starts reading the (1-K)Nth word at the same time, and if the switch (7) is switched at any time within the time Tw from the start of reading, the time (corresponding to the time Td) is reached. 1-K) N words are to be skipped, and when T one hour has passed since the start of reading, the second reading circuit (6
) reads the Nth word and excess data is discarded.

Problems with the Prior Art In the conventional signal processing device as described above, data loss or overlap occurs corresponding to the difference time Td shown in equation (4), but the allowable upper limit of this time Td is is set at 50~'10tnS, and for speech, it is set at 5~7mS to reduce intelligibility due to missing consonants, etc.
It is said that Therefore, in order to change the time Td, it is necessary to change the write time T- depending on the processing target, but this has the problem of increasing the memory capacity.

OBJECTS OF THE INVENTION In view of the above, an object of the present invention is to provide an audio signal processing device that can arbitrarily set the amount of overlap or omission of data according to the processing target without increasing the memory capacity. It is about providing.

SUMMARY OF THE INVENTION The present invention provides an audio signal processing device that writes a digitized audio signal into a memory and reads it from the memory at a speed different from the writing speed. first and second read control means for controlling read; read interval setting means for setting the interval between successive positions of the first and second read control means; and write position and first and second read control means for controlling the write control means. The first readout position is compared with the readout position of the second readout control means.
and a second comparison means, and the first and second readout control means are respectively controlled by comparison outputs of the first and second comparison means.

Embodiment Hereinafter, an embodiment of the audio signal processing apparatus according to the present invention will be described with reference to FIGS. 1 to 6.

FIG. 1 shows the configuration of an embodiment of the present invention. In this Figure 1, the audio signal supplied from the input terminal (1) is A/
It is converted into PCM in the D converter (2) and supplied to a memory such as a 64-bit dynamic RAM (January 3), for example. (11) and (12) are a write control signal generator and a read control signal generator, respectively; Generates write and read clocks. (14) and (15) and (16) are a write address counter and first and second read address counters, respectively, and the write address counter (14) is supplied with the output of the write control signal generator (11). The output of is supplied as a write address signal to the write control terminal (9) of the memo January 3), and the output of the read control signal generator (12) is supplied to the first and second read address counters (12). The outputs of 15) and (16) are respectively supplied to two read control terminals (3q) and (3r) of the memory (3) as first and second read address signals.

(17) and (18) are adder circuits, (19) is an address offset circuit, and both adder circuits (17) and (1
8) has first and second read address counters (15
) and (16), respectively, are supplied with the first and second read address signals, and the address offset circuit (19) is supplied with appropriately set address offset 1" data. Both adder circuits (17) The outputs of (18) and (18) are supplied to second and first read address counters (16) and (15), respectively.

(21) and (22) are first and second address comparison circuits, (23) and (24) are metastable multi-by-breaks (hereinafter abbreviated as MMV), and (25) and (26) are differentiating circuits. Then, both address comparison circuits (21) and (2
2) are supplied with the outputs of the reread address counters (15) and (16), respectively, and the output of the write address counter (14) is supplied to both address comparison circuits (21).
and (22) in common. Address comparison circuit (
2]) and (22) are supplied to MMVs (23) and (24), respectively, and both MMVs (23> and (24)
The outputs of are supplied to first and second read address counters (15) and (16) via differentiating circuits (25) and (26), respectively. (27) is a crossfade circuit, (28) is a crossfade control signal generator,
The cross-fade circuit (27) is supplied with read data from both output terminals (30) and (3p) of the memo January 3), and is also supplied with the output of the cross-fade control signal generator (28). This control signal generator (28) has M
The outputs of MV (23) and (24) are supplied. The output of the cross-fade circuit (27) is supplied to the D/A converter (8), and its output is taken out to the output terminal (9).

Next, the operation of this embodiment will be explained with reference to FIGS. 2 to 6.

In the present invention, the memo 3) has a capacity of N words and is equivalent to a memo whose beginning and end are connected in a ring by controlling the writing and reading positions, as shown in FIG. data is written into this equivalent annular memory 13), and the subsequent output is performed in two systems. The data write position is represented by W, and the data read positions of the two systems are represented by R1 and R2, respectively. Before starting the operation, the writing position W and the first
It is assumed that the readout positions R1 are located at both ends of the same diameter of the annular memory (3), and the second readout position R2 is delayed by 90° from the first readout position R1.

The ratio of the data read frequency fR from the memory (3) to the data write frequency to the memo (3), that is, the above K is 1.
, the relative relationship between the write position W and the read positions R1, R2 does not change even during operation of the device.

If K>1, after the device starts operating, the first readout position R
1 gradually approaches the write position Hw, and the second read position R2 moves away from the write position W. At this time, only data from the first read position R1 is used.

As shown in FIG. 4, when the angular distance between the first read position R1 and the write position W reaches 90°, the data from the first read position R1 starts to fade out, and at the same time the data from the second read position R1 starts to fade out. Start fading in data from read position R2. When the crossfade is completed after a predetermined period of time, both the Z rereading positions R1 and R2 advance by an angular distance φ to become R1' and R2', respectively, and the Z rereading positions R1 and R2 move to the second readout position R.
Only data from 2' is used. The first read position R1' is 180°, that is, the second read position R2'
It moves to position R1'' which is delayed by an angular distance of 90° from .

Thereafter, the data from R2' is used until the angular distance between the read position R2' and the write position W of the hook 2 becomes 90°,
When the angular distance between the two reaches 90 degrees, loss fading is performed as described above, and the faded out reading position is moved back 180 degrees.

When K<1, contrary to the above, the write position W approaches the read position, so as shown in FIG.
The second read position R2 is advanced by 90' relative to the first read position R1 where data is first used.

As shown in FIG. 6, when the angular distance between the write position W and the first read position R1 reaches 90°, cross-fade between the re-read positions R1 and R2 is performed in the same way as in the above case. At the end of the cross-fade, both re-read positions advance by an angular distance φ to become R1' and R2', respectively, and data from the second read-out position R2' is used.

Then, the first read position R,/ moves 180 degrees, that is, to a position R1'' which is 90 degrees ahead of the second read position R2'.

Thereafter, data from R2' is used until the angular distance between the second read position R2' and the write position W becomes 90°,
When the angular distance between the two reaches 90°, a crossfade is performed, and the readout position that faded out becomes 180°.
Advance.

In the embodiment shown in FIG.
The settings for address counter (14) and (
15) and (16), and an offset value corresponding to the above-mentioned 90° is set by the address offset circuit (19).

After the start of the operation, as shown in FIG. 4 or FIG. ) and the first read address counter (1
The first address comparison circuit (21) which compares both address signals from 5) detects the predetermined allowable address difference of 90°, and the first MMV (23) is triggered by the detection signal.

MMV (23) is calculated at time t1 (as shown in FIG. 2A).
(time point when an address difference equivalent to 90° occurs) to t2 (90°
A pulse (2) that determines the cross-fade period (the point in time when the address difference is equivalent to 10φ) is supplied to the differentiating circuit (25) and the cross-fade control signal generator (28). The control signal generator (28) generates control signals @ and cuff fade circuit (
27) and both output terminals (3o
) and (3p) are converted into analog signals by the D/A converter (8), and are digitally processed so that the time-amplitude characteristics shown in Figure 2 C and D are obtained. , a crossfade is performed. On the other hand, MMV (23
) is supplied from the differentiating circuit (25) to the first read address counter (15), and the address signal of this counter (15) is applied to the second read address counter (16). It is preset to a new address obtained by adding the address and the 90° equivalent offset value of the address offset circuit (19) by the adder circuit (18). This presetting of the address signal corresponds to a movement of the first read position in FIGS. 4 and 6 by 180 degrees from R1' to R1''.

As the device continues to operate, a second address comparison circuit (2
2) detects a predetermined difference (in this case, an address difference equivalent to 90°) between both address signals from the write address counter (14) and the second read address counter (16), the detection signal causes the second (7) ) MMV (24) is triggered. The MMV (24) supplies a pulse (2) defining a cross-fade period from time t3 to t4 as shown in FIG. 2B to a differentiating circuit (26) and a cross-fade control signal generator (28).

The control signals 0 and 2 are supplied from the control signal generator (28) to the cross-fade circuit (27), and the above-mentioned time points t1 to t
Cross-fade signal processing opposite to that in case 2 is performed. Also, the output of MMV (24) from the differentiating circuit (26)
The differential signal at the trailing edge of the second read address counter (1
6), and similarly to the above, the address signal is shifted by the value of the adder circuit (17), that is, 180°, and preset.

In the above explanation, address counters (14), (1
The difference in address signals (address offset amount) in 5) and the predetermined allowable address difference between the write address and the read address were set to be equivalent to 90" of the circular memory (3),
Needless to say, both can be set arbitrarily by controlling the address offset circuit (19).

That is, as the address offset amount is increased or decreased, the amount of overlamp or dropout can be increased or decreased.

Effects of the Invention As detailed above, according to the present invention, the amount of data overlap and loss can be arbitrarily set without increasing the memory capacity, so optimal signal processing can be performed depending on the processing target. It is possible to obtain an audio signal processing device that performs the following steps.

[Brief explanation of the drawing]

1 and 2 are block diagrams and time charts thereof showing one embodiment of the audio signal processing device according to the present invention;
6 to 6 are route maps for explaining the present invention, FIG. 7 is a block diagram showing a configuration example of a conventional audio signal processing device, and FIG.
FIG. 9 and FIG. 9 are route maps for explaining the same. (3) is memory, (14) is write address counter,
(15) and (16) are read address counters,
(19) is an address offset circuit, (21),
(22) is a comparison circuit, (27) is a crossfade circuit,
(28) is a crossfade control signal generator. Special opening HGI-29899 (7) Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] In an audio signal processing device that writes a digitized audio signal to a memory and reads it from the memory at a speed different from that at the time of writing, the audio signal processing device includes a write control means for controlling writing to the memory, and a writing control means for controlling reading from the memory. first and second read control means; read interval setting means for setting the interval between the read positions of the first and second read control means; and first and second comparison means for respectively comparing the readout position of the readout control means, and control the first and second readout control means, respectively, based on the comparison outputs of the first and second comparison means. An audio signal processing device characterized by: