JPS61296837A - Transmission and reception circuit in digital transmission system - Google Patents

Abstract

PURPOSE:To ensure decentralizing processing among terminal equipments in addition to centralized processing by giving the drive capability of a bus line to each transmission/reception circuit and driving a bus line synchronously with data transmission timing. CONSTITUTION:An oscillator 9 and a frequency divider 11 are operated to output a timing pulse (a) to a timing circuit 7. When a transmission signal (b) from a microcomputer 1 is outputted, a signal (d) is outputted from a D flip-flop circuit 7a. An EXOR gate outputs a signal (e) from the signals d, b, the result is inverted by an inverter 7c anc outputted to an AND gate 7d. A base signal (f) of a transistor (TR) 13 is outputted from the inverted signal, while the transmission signal (b) outputted from the microcomputer 1 is outputted as a base signal (c) of a TR 5 via a comparator 3. Thus, when the TR 4 is turned on, the TR 13 is turned on and when the TR 5 is turned off, the TR 13 is turned off and the transmission signal is outputted to a bus line 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field of the invention] The present invention relates to a digital transmission system such as a digital
The present invention relates to a transmitting/receiving circuit in an RZ transmission system.

[Technical Background and Problems of the Invention] FIG. 4 is a block diagram showing a schematic configuration of a home bus system as an example of a digital transmission system.

In this home bus system, a bus line 101 made of coaxial cables, metallic cables, etc. is installed in each home in advance, and the bus line 101 is connected to a home computer 103, various home appliances, a security system device, and a house control device. It connects various terminal devices 105 such as, and centrally manages these terminal devices 105. Furthermore, since the home bus system is a data transmission system within the home, a digital baseband transmission method that does not require a modulation/demodulation device is adopted in consideration of economical efficiency and ease of maintenance management.

Therefore, in order to obtain the drive ability of DC transmission, 5■
The DC voltage is applied to the line impedance supplying resistor 107.
is supplied to the bus line 101 via the bus line 101 to keep the bus line 101 active.

However, conventionally, the resistor 107 for supplying line impedance has been provided only in the home computer 1.3 or the so-called head end that functions as the main controller. There was a problem that not only the voltage was not supplied and the entire home bus system stopped functioning, but also that distributed processing among the terminal devices 105 could not be performed.

[Object of the Invention] The present invention has been made based on the above circumstances, and an object thereof is to provide a transmitting/receiving circuit in a digital transmission system that can reliably perform distributed processing.

[Summary of the Invention] A digital transmission system comprising a transmitting/receiving circuit that transmits and receives data by digital baseband transmission and having a plurality of terminal devices connected to a bus line, the transmitting/receiving circuit at least transmitting the data. The gist is to include line drive means for activating the bus line at times.

[Effects of the Invention] According to the present invention, each transmitter/receiver circuit has the ability to drive a bus line, and the bus line can be driven in synchronization with the data transmission timing. Distributed processing between devices can be reliably performed.

[Embodiment of the invention] FIG. 1 shows an embodiment of the present invention (hereinafter referred to as the first embodiment)
FIG. 2 is a block diagram showing the configuration of the system, and FIG. 2 is a time chart.

The microcomputer 1 (hereinafter referred to as microcomputer) is a one-chip microcomputer for transmission control, and the microcomputer 1 outputs the transmission signal shown in FIG. 2 (B), which is supplied to the comparison circuit 3 and timing circuit 7. has been done.

In the comparator circuit 3, when a transmission signal of a certain level or higher is inputted, a signal C shown in FIG. 2(C) is outputted, and the transistor 5 is turned on and off by this signal C.

The timing circuit 7 includes the D flip 70 knob 7a and the EXO
It is composed of an R gate 7b, an inverter 7G, and an AND gate 7d.
) is generated and supplied to the base of the transistor 13.

A resistor 17 for supplying line impedance (for example, 100Ω) of the bus line 15 is connected to the emitter of the transistor 13. A DC voltage (for example, +5V) is applied to this resistor 17, and the transistor 5.
This resistor 17 is connected to the bus line 15 in synchronization with the on/off timing of 13, that is, the transmission timing of the transmission signal.
bus line 15 by passing a direct current according to the resistance value of
is driving.

One amplifier is a receiving amplifier, which receives the transmission signal transmitted to the bus line 15 as described above and supplies it to the microcomputer 1.

Next, the operation will be explained. When the power is turned on, the excavator 9 and the frequency divider 11 operate and output the timing pulse a shown in FIG. 2(A) to the timing circuit 7.

When the microcomputer 1 outputs the transmission signal s shown in FIG. 2(B), the D flip-flop 7a outputs the signal d shown in FIG. 2(D).

The EXOR gate outputs the signal e shown in FIG. 2(E) from the output signal d of the D flip-flop 7a and the above-mentioned transmission signal, and this signal is inverted by the inverter 7G and output to the AND gate 7d. .

The AND gate 7d outputs the base signal f of the transistor 13 shown in FIG. 2(F) from the transmission signal S and the signal inverted by the inverter 7C.

On the other hand, the transmission @b outputted from the microcomputer 1 is outputted as the transistor 50 base signal C shown in FIG. 2(C) via the comparison circuit 3.

Therefore, as can be understood from FIG. 2, when the transistor 5 is on, the transistor 13 is also on, and when the transistor 5 is off, the transistor 13 is also off, so that the transmission signal is not transmitted to the bus line 15. Output. Further, this transmission signal is input to the microcomputer 1 via an amplifier 19.

Note that there is a delay time between the signal C shown in Figure 2 (C) and the signal f shown in Figure 2 (F), but this is due to the influence of the capacitive load etc. floating in the entire system. This is done in consideration of the fact that the transmission signal waveform is rounded due to this, and this delay time is appropriately set according to the value of the capacitive load, etc.

In this way, in this embodiment, line drive capability is given to the transmitter/receiver circuit of each terminal device only when transmitting a transmission signal, so even if the aforementioned home computer or head end breaks down, distributed processing between each terminal device can be ensured. can be done.

It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, the oscillator 9 may be an oscillator within the microcomputer 1, and the configuration of the timing circuit 7 is not limited thereto either.

Furthermore, the resistor 17 for supplying line impedance is inserted between the emitter of the transistor 13 and the DC power supply, but if sufficient impedance can be supplied to activate the bus line 15, the resistor 17 for supplying line impedance can be inserted between the collector side and the base side of the transistor 13. May be connected.

FIG. 3 is a block diagram showing another embodiment of the present invention.

This embodiment differs from the first embodiment in that a line drive capability, that is, a resistor 17 as a line input driver is provided on each side of the transmitting/receiving circuit of each terminal device. The ratio of the resistor 17 connected to the bus line 15 changes, and the bus line 15
This avoids the problem of lowering the voltage level.

For this reason, in this embodiment, as shown in FIG. 3, an electromagnetic relay 21 is inserted between the transmitting/receiving circuit 20 and the bus line 15.

This electromagnetic relay 21 receives an excitation current from a power source 23, and when the power source 23 is turned off, its contacts are opened, thereby disconnecting the transmitting/receiving circuit 20 from the bus line 15.

Then, when the power supply 23 is turned on, the relay coil is excited and its contacts are closed, and the resistor 17 is connected to the bus line 15 again.

In this way, in this embodiment, the power supply 23 of the transmitting/receiving circuit 20
Since the transmission/reception circuit 20 is disconnected from the bus line 15 when the power supply 23 is turned off, the resistance 17 is disconnected when the power supply 23 is turned off.
is reliably disconnected from the bus line. Therefore, a drop in the voltage level of the bus line 15 can be avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a timing chart for the embodiment shown in FIG.
FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention;
FIG. 4 is a block diagram showing a schematic configuration of a conventional home bus system. 1... Microcomputer 3... Comparator 5.7... Transistor 7... Timing circuit 15... Bus line 17... Resistor 21... Electromagnetic relay

Claims (2)

[Claims] (1) In a digital transmission system comprising a transmitting/receiving circuit that transmits and receives data by digital baseband transmission and having a plurality of terminal devices connected to a bus line, the transmitting/receiving circuit is configured to transmit data via the bus line at least when transmitting the data. A transmitting/receiving circuit in a digital transmission system, comprising line drive means for activating a line. (2) The transmitter/receiver circuit in a digital transmission system according to claim 1, wherein the line drive means includes means for disconnecting the line drive means from the bus line when the power is turned off.