JPH07249973A - Electronic equipment - Google Patents

Abstract

PURPOSE:To obtain an electronic equipment capable of surely preventing the generation of a latch-up state in a signal receiving side circuit when a power supply for the circuit is turned off and executing stable control. CONSTITUTION:When a voltage drop detecting circuit 5 detects the OFF of the power supply 4 for the signal receiving side circuit 2, an output from a signal transmitting side circuit 1 is turned to high impedance by a 3-state buffer 6 based upon the detection output of the circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention comprises at least two circuits, each of which is supplied with a power supply voltage from a separate power supply.
The present invention relates to an electronic device that transmits and receives a signal between the circuits, and more particularly, to an electronic device that is improved so as to prevent latch-up of the signal receiving circuit when the power of the signal receiving circuit is turned off.

[0002]

2. Description of the Related Art Various electronic devices are known which are provided with a plurality of circuits each of which is supplied with electric power from a separate independent power source and which are configured to transmit and receive signals between the circuits. There is.

FIG. 5 shows a conventional example of such an electronic device. In FIG. 5, a circuit 1 (circuit A) on the transmission side and a circuit 2 (circuit B) on the reception side are provided, and transmission is performed. The circuit 1 on the side is driven by being supplied with the power supply voltage from the power supply 3, and the circuit 2 on the receiving side is driven by being supplied with the power supply voltage from the power supply 4 and is transmitted from the circuit 1 on the transmission side to the circuit 2 on the reception side. It is configured to send signals via 7.

By the way, in the conventional apparatus shown in FIG. 5, even if the power source 4 of the receiving side circuit 2 is turned off, the power source 3 of the transmitting side circuit 1 is turned off unless the power source 3 of the transmitting side circuit 1 is turned off. A signal is transmitted to the receiving side circuit 2 via the signal line 7. As a result, the integrated circuit (IC) in the circuit 2 on the receiving side is latched up by the signal transmitted from the circuit 1 on the transmitting side even if the power source voltage is not applied from the power source 4, and is damaged as a result. There were times when it happened.

To solve this problem, the following two methods have hitherto been taken.

One of them is a method of inserting a resistor 13 into a signal line 7 connecting the circuit 1 and the circuit 2 as shown in FIG. According to this method, when only the power supply 4 of the circuit 2 is turned off, the voltage of the signal output from the circuit 1 to the circuit 2 is divided by the resistor 13 and the internal impedance of the input port of the circuit 2, As a result, the voltage applied to the input port of the IC in the circuit 2 is lowered, and the current flowing from the circuit 1 to the circuit 2 is reduced, so that the IC in the circuit 2 can be prevented from latching up.

However, in this case, the input port of the IC in the circuit 2 is in an unstable state, and there is a problem that stable control cannot be performed by this method.

As another method, as shown in FIG. 7, a voltage drop detection circuit 5 for detecting OFF of the power source by monitoring the output voltage of the power source 4 is provided in the power source 4 of the receiving side circuit 2. A method of providing a central processing unit (CPU) 12 for forcibly controlling the signal output from the circuit 1 on the transmission side to be OFF based on the detection output of the voltage drop detection circuit 5 in the circuit 1 on the transmission side. Is.

However, in the case of this method, the receiving side circuit 2
It takes time for the signal output from the circuit 1 on the transmission side to be turned off by the software processing by the CPU 12 after the power supply 4 of the circuit is turned off, which may cause the IC in the circuit 2 on the reception side to latch up. Is still left.

[0010]

As described above, in the conventional apparatus of this type, only the power source of the circuit on the receiving side is O.
In the case of FF, the IC in the receiving side circuit may be latched up and damaged due to the voltage of the signal transmitted from the transmitting side circuit to the receiving side circuit.

In order to prevent this, 1) a method of inserting a resistor into a signal line connecting a circuit on the transmitting side and a circuit on the receiving side 2) turning off the power supply of the circuit on the receiving side to the circuit on the receiving side A method of providing a detecting means and a CPU for forcibly turning off the output of the transmitting side circuit by software processing based on the detection output of the detecting means is considered, but 1) According to the method of (2), although the IC in the circuit 2 can be prevented from latching up, there is a problem that the input port of the IC in the circuit 2 becomes unstable. There is a problem that it takes time until the signal output from the circuit on the transmission side is turned off by the software processing, which may cause the IC in the circuit on the reception side to latch up.

Therefore, the present invention provides an electronic device capable of reliably preventing latch-up in the circuit of the signal receiving side and performing stable control when the power of the circuit of the signal receiving side is turned off. The purpose is to

[0013]

In order to achieve the above object, the present invention comprises at least two circuits each of which is supplied with a power supply voltage from a power supply of a different system, and which transmits and receives a signal between the circuits. In the device, a low voltage detection that generates a detection output when the power applied to the signal transmitting side circuit of the circuit is turned on and the power applied to the signal receiving side circuit of the circuit is turned off Means are provided, and the circuit on the signal transmission side is provided with control means for setting the transmission output of the circuit on the signal transmission side to high impedance based on the detection output of the low voltage detection means.

[0014]

According to the present invention, the low voltage detecting means detects that the power applied to the circuit on the signal transmitting side is on and the power applied to the circuit on the signal receiving side is off, and based on the detected output. The control means controls the transmission output of the circuit on the signal transmission side to a high impedance so that the signal does not flow from the circuit on the signal transmission side to the circuit on the signal reception side to protect the circuit on the signal reception side.

Here, the control means is provided at the output of the circuit on the signal transmission side, and sets the transmission output of the circuit on the signal transmission side to high impedance based on the detection output of the low voltage detection means. Can be provided.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an electronic device according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an electronic device according to the present invention. In FIG. 1, parts having the same functions as those of the conventional device shown in FIG. 5 are given the same reference numerals as those used in FIG. 5 for convenience of explanation.

The embodiment shown in FIG. 1 comprises a circuit 1 on the transmitting side (circuit A) and a circuit 2 on the receiving side (circuit B),
The circuit 1 on the transmission side is driven by being supplied with a power supply voltage from the power supply 3, and the circuit 2 on the receiving side is driven by being supplied with the power supply voltage from the power supply 4 to transmit a signal from the circuit 1 on the transmission side to the circuit 2 on the reception side. It is arranged to transmit a signal via line 7.
Further, a voltage drop detection circuit 50 is connected to the power supply 4, and the voltage drop detection circuit 50 detects that the power supply voltage output from the power supply 4 is equal to or lower than a predetermined voltage, that is, the power supply 4 is turned off. In this case, a detection output is generated.

The voltage drop detection circuit 50 may be provided on either the circuit 1 side on the transmission side or the circuit 2 side on the reception side. The power source of the voltage drop detection circuit 50 is that of the circuit 1 on the transmission side. Take it from the power supply 3.

After all, the voltage drop detecting circuit 50 detects that the power source 3 is ON and the power source voltage output from the power source 4 is equal to or lower than a predetermined voltage, that is, the power source 4 is OFF.
In this case, a detection output is generated.

Further, in the circuit 1 on the transmission side, a three-state buffer 6 for controlling the signal output of the circuit 1 on the transmission side to a high impedance based on the detection output output from the voltage drop detection circuit 50 is provided.

According to such a configuration, the circuit 1 on the transmitting side is
When the power supply 3 for supplying the power supply voltage to the ON side is turned on and the power supply 4 for supplying the power supply voltage to the receiving side circuit 2 is turned off, the output side of the 3-state buffer 6 becomes high impedance, which causes the signal line 7 to pass through. The current flowing from the circuit 1 on the transmitting side to the circuit 2 on the receiving side is eliminated through this, and the latch-up of the IC in the circuit 2 on the receiving side is reliably prevented.

FIG. 2 shows another embodiment of the present invention. In the embodiment shown in FIG. 2, the signal is the signal line 7
The present invention is applied to an electronic device which is transmitted not only from the circuit 1 to the circuit 2 via the signal line but also from the circuit 2 to the circuit 1 via the signal line 10.

In the embodiment shown in FIG. 2, in addition to the configuration shown in FIG. 1, the power supply voltage output from the power supply 3 is equal to or lower than a predetermined voltage, that is, the voltage for detecting when the power supply 3 is turned off. The voltage drop detection circuit 8 is further provided, and the circuit 2 is provided with a three-state buffer 9 that controls the signal output of the circuit 2 to high impedance based on the detection output output from the voltage drop detection circuit 8.

In this case, the voltage drop detection circuit 8 is powered from the power supply 4 of the transmission side circuit 2.

In such a configuration, the voltage drop detection circuit 50 detects when the power supply 3 is ON and the power supply voltage output from the power supply 4 is equal to or lower than a predetermined voltage, that is, when the power supply 4 is OFF. If a detection output is generated.

Further, in the voltage drop detection circuit 8, the power source 4 is turned off.
The power supply voltage N and the power supply voltage output from the power supply 3 are equal to or lower than a predetermined voltage, that is, the case where the power supply 3 is turned off is detected, and a detection output is generated in this case.

When a detection output is generated from the voltage drop detection circuit 50, that is, the power supply 3 for supplying the power supply voltage to the circuit 1 is turned on and the power supply 4 for supplying the power supply voltage to the circuit 2 is turned on.
Is turned off, the output side of the 3-state buffer 6 becomes high impedance, whereby the current flowing from the circuit 1 to the circuit 2 via the signal line 7 disappears, and the IC in the circuit 2 is surely latched up. To be prevented.

When a detection output is generated from the voltage drop detection circuit 8, that is, the power supply 4 for supplying the power supply voltage to the circuit 2 is turned on and the power supply 3 for supplying the power supply voltage to the circuit 1 is O.
In the state of FF, the output side of the 3-state buffer 9 becomes high impedance, which causes the signal line 1
There is no current flowing from circuit 2 to circuit 1 through 0,
Latch-up of the IC in the circuit 1 is reliably prevented.

FIG. 3 shows still another embodiment of the present invention. In this embodiment as well, as in the embodiment shown in FIG. 2, not only the signal is transmitted from the circuit 1 to the circuit 2 via the signal line 7, but also from the circuit 2 to the circuit 1 via the signal line 10. To be

In the embodiment shown in FIG. 3, the circuit 1
The voltage drop detection circuit 11 is provided in common for the power supply 3 that supplies the power supply voltage to and the power supply 4 that supplies the power supply voltage to the circuit 2. In this case, the voltage drop detection circuit 11 can take the power supply voltage from either the power supply 3 or the power supply 4,
When the power supply voltage output from either the power supply 3 or the power supply 4 drops below a predetermined voltage, a detection output is generated.
The detection output output from the voltage drop detection circuit 11 is simultaneously applied to the 3-state buffer 6 of the circuit 1 and the 3-state buffer 9 of the circuit 2, and the output sides of the 3-state buffer 6 and the 3-state buffer 9 are simultaneously set to high impedance. To do.

With such a configuration, the circuit can be greatly simplified as compared with the embodiment shown in FIG.

FIG. 4 shows the voltage drop detection circuit 1 shown in FIG.
1 shows a concrete circuit example of No. 1. The circuit shown in FIG. 4 includes two diodes 20 and 21 and an AND gate circuit 22. In the circuit shown in FIG. 4, the power supply voltages output from the power supply 3 and the power supply 4 are applied as power supplies to the AND gate circuit 22 via the diodes 20 and 21, respectively, and the power supply 3 and the power supply are further input to the AND gate circuit 22. Apply the output voltage of 4 directly. Here, when either of the power supply voltages output from the power supply 3 and the power supply 4 drops below a predetermined voltage, the output of the AND gate circuit 22 becomes a low level.
The output of the D-gate circuit 22 controls the output sides of the 3-state buffer 6 and the 3-state buffer 9 so as to be simultaneously in high impedance.

[0034]

As described above, according to the present invention, it is confirmed by the low voltage detecting means that the power source applied to the signal transmitting side circuit is turned on and the power source applied to the signal receiving side circuit is turned off. Since the control means controls the transmission output of the signal transmitting side circuit to a high impedance based on the detected output, even if the power supply of the signal receiving side circuit is turned off, the signal receiving side circuit It is possible to reliably prevent the latch-up of and to perform stable control.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an electronic device according to the present invention.

FIG. 2 is a block diagram showing another embodiment of an electronic device according to the present invention.

FIG. 3 is a block diagram showing still another embodiment of the electronic device according to the present invention.

FIG. 4 is a circuit diagram showing an example of the voltage drop detection circuit shown in FIG.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a block diagram showing another conventional example.

FIG. 7 is a block diagram showing still another conventional example.

[Explanation of symbols]

 1 circuit (circuit A) 2 circuit (circuit B) 3 power supply 4 power supply 5, 8, 11, 50 voltage drop detection circuit 6, 9 three-state buffer 7, 10 signal line 12 central processing unit (CPU) 13 resistor 20, 21 diode 22 AND gate circuit

Claims (2)

[Claims] 1. An electronic device comprising at least two circuits each of which is supplied with a power supply voltage from a power supply of a different system, and which transmits and receives a signal between the circuits, in addition to the circuit on the signal transmission side of the circuits. A low voltage detecting means for generating a detection output when the power applied to the signal receiving side circuit in the circuit is turned off, and the low voltage detecting means is provided in the signal transmitting side circuit. An electronic apparatus comprising: a control unit that sets a transmission output of the circuit on the signal transmission side to a high impedance based on a detection output of the detection unit. 2. The three-state buffer which is provided at the output of the circuit on the signal transmission side, and sets the transmission output of the circuit on the signal transmission side to high impedance based on the detection output of the low voltage detection means. The electronic device according to claim 1, further comprising: