KR880001656B1 - Signal transfer control device of elevator - Google Patents

Abstract

The elevator control signal is transmitted in a single transmission line (12) by installing a signal transmitter (13) in a cage and a signal demodulator (11) in a control room. The signal transmitter (13) comprises switches, latch circuits, a parallel/serial data converter, a demultiplier, a counter, and a decoder so that parallel data generated in the cage are converted to serial data and transmitted to the control room through a single transmission line. The signal demodulator includes a serial/parallel data converter and a decoder so that the received serial data is converted to parallel form in the control room.

Description

Signal transmission control device of elevator

1 is a schematic configuration diagram of a device of a conventional elevator.

2 is a schematic configuration diagram of an elevator apparatus to which the present invention is applied.

3 is a detailed circuit diagram of a signal transmission device for transmitting signals of various switches and call buttons in a cage to a transmission line in the present invention.

4 is a detailed circuit diagram of a signal demodulation device for detecting various signals in a cage received from a transmission line in the present invention and supplying control signals to the control circuit.

5 is a timing chart for explaining the circuit operation of each part of the present invention.

6 is a truth table for explaining the circuit operation of each part of the present invention.

* Explanation of symbols for main parts of the drawings

11 signal demodulation device 13 signal transmission device

12: single signal transmission line 14, 15, 16, 17: latch circuit

18 parallel-to-serial converter 19 divider

20: counter 21: decoder

29, 30, 31, 32: de-flip-flop 24: series-to-parallel converter

25: divider 26: clock generator

27: counter 28: decoder

The present invention relates to a transmission control apparatus for transmitting signals of various switches and call buttons attached to a cage in an elevator to a control panel.

In the conventional apparatus, as shown in FIG. 1, a plurality of power lines and signal transmission lines are connected as a means of communication communication between the cage 8 and the control panel 1, which saves a lot of time and money during installation and repair. In addition, there is a problem that the power consumption is increased by increasing the load due to the large size of the mobile cable.

In view of the above, the present invention converts these signals into signals capable of serial transmission and transmits them to the control panel using only a single wire in order to transmit signals related to the state of various switches and the call button of the cage to the control panel using only several wires. The control panel decodes the serial transmission signal so that the state of various switches and call buttons attached to the cage can be easily identified, which will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the signal transmission device 13 is connected to various switches and buttons 9 installed in the cage 8, and the control panel (1) is connected to the signal transmission device 13 through a single signal transmission line 12. 1) The signal demodulation device 11 installed inside is connected.

)에 복호기(21)의 출력단자(Oψ), (O₁), (O₂),(O₃)를 연결하고, 상기 랫치회로부(14), (15), (16), (17)의 각 출력단자 (Oψ), (O₁), (O₂),(O₃),(O₄), (O₅),(O₆),(O₇)는 공접하여 병렬-직렬 변환기(18)의 입력단자(Dψ-D₇)에 연결하고, 상기 복호기(21)의 입력단자(Aψ-A₃)에 출력단자(Qψ-Q₃)가 접속된 카운터(20)의 클럭신호 단자(

)에는 분주기(19)를 통하여 상기 병렬-직렬 변환기(18)의 입, 출력 제어단자(

)를 연결하여 구성한다.As shown in FIG. 3, the signal transmission device 13 includes the enable output terminals of the latch circuits 14, 15, 16, and 17.

), And output terminals (Oψ), (O ₁ ), (O ₂ ), and (O ₃ ) of the decoder 21, and the latch circuits 14, 15, 16, and 17 of the Each output terminal (Oψ), (O ₁ ), (O ₂ ), (O ₃ ), (O ₄ ), (O ₅ ), (O ₆ ), (O ₇ ) are shared and parallel-to-serial converter (18) a clock signal terminal of) the counter 20 is coupled to an input terminal (Dψ _D-7), and to an input terminal (Aψ _a-3) of the decoder 21, the output terminal (Qψ-Q ₃₎ connected to the (

) Input and output control terminals () of the parallel-to-serial converter 18 through a divider 19.

) To connect.

)에는 분주기(25)및 클럭발생기(26)를 통하여 상기 직렬-병렬 변환기(24)의 클럭입력단자(CP)를 연결하고, 상기 디 플립플롭(29),(30), (31), (32)의 출력단자(Oψ-O₇)는 통상의 제어회로부(2)에 연결하여 구성시킨다.In addition, the signal demodulator 11 has an input terminal A and an output terminal (Q) 23 and a clock input terminal (CP) 22 of the parallel-to-serial converter 18 as shown in FIG. The output terminals Qψ-Q ₇ of the serial-to-parallel converter 24 to which the clock input terminal CP is connected are de-flip flops (DF / F) 29, 30, 31 and 32, respectively. Is connected to the input terminals Dψ-D ₇ and the output terminals Oψ and (O ₁ ) are respectively connected to the clock input terminals CP of the de-flipped flops 29, 30, 31, and 32, respectively. (A ₂ ), (A ₁ ), (A ₂ ), and (A ₃ ) of the decoder 28 to which (O ₂ ) and (O ₃ ) are connected, the output terminals (Qψ) of the counter 27, (Q ₁ ), (Q ₂ ), and (Q ₃ ), and the clock signal terminal thereof

) Is connected to the clock input terminal CP of the serial-to-parallel converter 24 through a divider 25 and a clock generator 26, and the de- flip-flops 29, 30, 31, The output terminal (Oψ-O ₇ ) of (32) is configured in connection with the normal control circuit section (2).

Reference numeral 3 denotes a group of signal transmission lines, 4 denotes a machine room bottom, 5 denotes a drive unit, 6 denotes a rope, 7 denotes a power control line, 10 denotes a weight, Vcc denotes a DC power supply, and I ₁ and I ₂ denote inverters. .

)는 로우레벨 상태일때에 입력된 데이타를 출력하고, 하이레벨 일때에는 출력단자(Oψ-O₇)에 나타나는 신호 상태를 고 임피던스로 만들어 병렬-직렬 변환기(18)와의 연결을 차단하게 된다.Referring to the effects of the present invention configured as described above are as follows. First, the operation state of each element used in the present invention will be described. The latch enable terminal LE of the latch circuits 14, 15, 16, and 17 has an input terminal Dψ- in a high level state. The data is inputted to D ₇ ). Since the power supply Vcc is always supplied to the terminal LE, signals from various switches and call buttons 9 installed in the cage 8 are being input. Enable output terminal

) Outputs the input data at the low level, and makes the signal state appearing at the output terminal (Oψ-O ₇ ) high impedance to cut off the connection to the parallel-to-serial converter 18 at the high level.

)가 분주기(19)의 출력단자(Q)에 접속되어 카운트 동작을 하게되며, 단자(MR₁), (MR₂)는 모두 하이레벨 일때에 출력단자(Qψ), (Q₁), (Q₂),(Q₃)가 로우 상태로 되어 리세트 되므로, 복호기(21)의 출력단자(O₄)가 로우 상태로 될때에 인버터(I₁)를 통하여 하이신호가 입력되어 리세트 상태가 된다.The counter 20 is a clock signal terminal (

) Is connected to the output terminal Q of the divider 19 to perform a counting operation. The terminals MR ₁ and MR ₂ are all at the high level, and the output terminals Qψ, Q ₁ , and ( Since Q ₂ ) and (Q ₃ ) are reset to the low state, when the output terminal O ₄ of the decoder 21 goes low, a high signal is inputted through the inverter I ₁ to reset the state. do.

),(

)신호가 로우 상태일때에 복호되므로 접지시킨 것이며, 입력단자(Aψ-A₃) 는 카운터(20)의 출력단자((Oψ-O₁₅)중의 하나만을 로우 상태로 만들어 랫치회로부 (14), (15), (16), (17) 의 인에이블 출력단자(

)로 보내게 된다. 즉 카운터(20)와, 복호기(21)는 케이지의 각종스위치 및 호출보턴으로부터의 신호 상태를 입력하는 랫치회로부(14), (15), (16), (17)와 병렬- 직렬 변환기(18)의 동기를 맞추어 랫치회로부(14), (15), (16), (17)가 순차적으로 동작할수 있도록 하기 위한 랫치(14), (15), (16), (17)의 인에이블 출력단자(

)에 제어신호를 공급하기 위한 것이다.The decoder 21 has a terminal (

), (

) Signal is grounded because it is decoded when the signal is in a low state, and the input terminal (Aψ-A ₃ ) makes only one of the output terminals ((Oψ-O ₁₅ ) of the counter 20 low. Enable output terminals (15), (16) and (17)

Will be sent). That is, the counter 20 and the decoder 21 are connected to the latch circuits 14, 15, 16, and 17 and the parallel-to-serial converter 18 for inputting signal states from various switches and the call button of the cage. Enable output of latches 14, 15, 16, and 17 to allow latch circuits 14, 15, 16, and 17 to operate sequentially in synchronization with Terminals(

) To supply a control signal.

가 제5도의 A부분과 같이 로우 상태일때, 입력단자(Dψ-D₇)에 랫치회로부(14), (15), (16), (17)의 출력단자(Oψ-O₇)로부터 데이타가 입력되며, 이 데이타(Dψ-D₇)들은 단자(

)가 제5도의 B 부분과 하이 상태이고, 클럭발생기(26)의 클럭펄스 신호가 병렬- 직렬 변환기(18)의 클럭 입력단자(CP)로 하나씩 입력될때마다 시프트가(shift)되어 출력단자(Q)를 통하여 데이타가 전송 선로(23)에 실리게 된다.The parallel-to-serial converter 18 has input and output control terminals.

Is the data from the output terminal (Oψ-O ₇₎ of the latch circuit 14, 15, 16, 17 on when a low state, as a separate part A fifth input terminal (Dψ-D ₇₎ The data (Dψ-D ₇ )

) Is high with the portion B of FIG. 5 and each time the clock pulse signals of the clock generator 26 are input one by one to the clock input terminal CP of the parallel-to-serial converter 18, the output terminal ( Through Q), data is carried on the transmission line 23.

)의 신호는 제5도에 나타낸 바와같이 적당한 크기의 분주율을 가지는 분주기(19)를 통하여 입력된다.Here, eight clock pulses are required in order for one byte of data Dψ-D _{7 to be} loaded on the transmission line 23, and a terminal for controlling data input / output of the parallel-to-serial converter 18 (

Signal is input through a divider 19 having an appropriate division ratio as shown in FIG.

Referring to FIG. 3, an operation state of the signal transmission apparatus 13 according to the present invention using the device operated as described above is as follows.

When power is initially supplied, the clock signal is input from the clock generator 26 in the control panel 1 to the clock input terminal CP of the divider 19 via the clock transmission line 22.

)에 카운트 클럭신호를 공급함과 동시에 병렬-직렬 변환기(18)의 입, 출력 제어단자(

)에 제어신호를 공급하게 된다. 따라서 카운터(20)는 단자(

)에 입력된 카운트클럭 신호를 카운트하여 출력단자(Qψ),(Q₁), (Q₂), (Q₃)를 통하여 복호기(21)의 입력단자(Aψ), (A₁), (A₂),(A₃)로 데이타 신호를 출력한다.This clock signal is divided into appropriate sizes by the divider 19 as shown in FIG.

At the same time, the input and output control terminals of the parallel-to-serial converter 18 are supplied.

) To supply the control signal. Therefore, the counter 20 is a terminal (

) Count the clock signal input to the) and the input terminals (Aψ), (A ₁ ), (A ₁ ) of the decoder 21 through the output terminals (Qψ), (Q ₁ ), (Q ₂ ), (Q ₃ ). ₂ ), (A ₃ ) outputs the data signal.

At this time, in order to counter 20 is to operate as shown in Figure 6, the decoder 21 in the decoding the input data, an output terminal (Oψ-O ₁₅₎ of the terminal from the terminal (Q ₁₅₎ (Oψ) Output low signal one by one.

However, since only four control signal terminals are required for the latch circuits 14, 15, 16, and 17, as shown in FIG. 6, the output terminal Q ₄ signal of the decoder 21 is low. When the signal is in the state, the terminals MR ₁ and MR ₂ of the counter 20 go high and are reset, and count again from the beginning, so that the output of the decoder 20 is four in one unit. Decryption output is sent out repeatedly, and the remaining output terminals (O ₅ -O ₁₅ ) are used for expansion.

)에 인가되므로 랫치회로부(14)는 입력단자(Dψ-D₇)에 입력된 데이타를 출력하여 병렬-직렬 변환기(18)에 공급한다.Here, as shown in FIGS. 5 and 6, when the output terminal (Oψ) signal of the decoder 21 is in a low state, the enable output terminal of the latch circuit unit 14 (

), The latch circuit unit 14 outputs the data input to the input terminal D? -D ₇ and supplies it to the parallel-to-serial converter 18.

)에 의하여 출력단자(Oψ-O₇)에 연결된 병렬-직렬 변환기(18)의 입력단자(Dψ-D₇)에 데이타를 공급한다.Subsequently, when the output terminal O ₁ signal of the decoder 21 becomes low, the enable output terminal of the latch circuit unit 15 (

The data is supplied to the input terminal Dψ-D ₇ of the parallel-to-serial converter 18 connected to the output terminal Oψ-O ₇ by means of.

)에 관한 제어동작도 상술한 바와 같은 동일 동작을 순차적으로 반복 하므로서, 병렬-직렬 변환기(18)는 랫치회로부(14), (15), (16), (17)에서 순차적으로 1바이트( Byte)단위로 입력된 데이타를 클럭 펄스가 하나씩 들어 올때마다 데이타 전송선로(23)를 통하여 케이지(8) 내부에 부착 설치된 각종 스위치 및 호출버턴(9)의 신호상태를 제어반(1) 내부에 설치된 신호 복조장치(11)에 전달하게 된다.On the other hand, the output terminals of the latch circuits 16 and 17 (

), And the parallel-to-serial converter 18 sequentially repeats one byte (byte) in the latch circuits 14, 15, 16, and 17 in sequence. Signals of various switches and call buttons 9 attached to the inside of the cage 8 through the data transmission line 23 are installed in the control panel 1 whenever the clock pulses are input one by one. It is transmitted to the demodulation device (11).

Next, the operation state of the device used in the signal demodulation apparatus will be described with reference to FIG.

The serial signal is inputted to the input terminal A of the serial-to-parallel converter 24 through the signal transmission line 23 from the signal transmission device, and converted into a parallel signal to the output terminals Qψ-Q ₇ . As shown in FIG. 6, the de-flip flops 29, 30, 31, and 32 are sequentially operated to supply a control signal to the control circuit unit 2. FIG.

Since the flip-flop can input data to the input terminal Dψ-D ₇ at the moment when the clock input terminal CP signal is changed from the low state to the high state, the clock input terminal CP is the decoder 28. It is connected to the output terminal (Oψ-O ₇ ) of respectively, and is operated instantaneously as shown in FIG. 5 and FIG. In addition, the enable output terminal (OE) signal of the flip-flop outputs the latched data when it is low, and when it is high, the output terminal (Oψ-O ₇ ) is set to high impedance so that it is always grounded. It is configured not to output data. The clock generator 26 also supplies clock signals to the serial-to-parallel converter 24 and the divider 25 of the signal demodulator, as well as to the parallel-to-serial converter 18 of the signal transmitter in the cage 8. The same clock signal is supplied to the period 19 to synchronize the signal demodulation device 11 with the signal transmission device 13, thereby achieving stable operation.

In addition, the serial-to-parallel converter 24 shifts the serial data inputted to the input terminal A to the output terminals Q? -Q ₇ whenever a clock signal is input to the terminal CP one by one.

That is, as shown in FIG. 5, the data is shifted by the eight clocks (clocks 9-16) from the clock generator 26 to fill the output terminals Q? -Q ₇ .

At this time, as shown in FIG. 5 and FIG. 6, the terminal (CP) rising edge of any one of the four de-flip flops (19), (30), (31), and (32) becomes , It accepts this data.

The operation of the counter 27 and the decoder 28 is the same as that of the counter and decoder used in the signal transmission apparatus, and description thereof will be omitted.

An operation state of the signal demodulation device 11 using the device operated as described above will be described with reference to FIG. 4 as follows.

When power is initially supplied, a clock pulse is generated from the clock generator 26 and input to the clock terminal CP of the serial-parallel converter 24 and the divider 25.

)에 카운트 클럭신호를 공급하게 되어 제6도에 나타낸 바와 같이 카운터(27)는 단자(

)에 입력된 카운트 클럭신호를 카운트하여 출력단자(Qψ),(Q₁), (Q₂), (Q₃)를 통하여 복호기(28)의 (Aψ),(A₁), (A₂), (A₃)로 데이타 신호를 송출하게 된다.At this time, as shown in FIG. 5, the frequency divider 25 divides the clock pulses from the clock generator 16 at an appropriate frequency division rate, so that the terminal of the counter 27 (

The count clock signal is supplied to the counter 27. As shown in FIG.

) The count outputs (Qψ counts the clock signal input _{on), (Q 1), (} Q 2), ((Aψ) of the decoder 28 through the _{Q 3), (A 1)} , (A 2) , (A ₃ ) transmits the data signal.

Therefore, the decoder 28 is in is the input to decode the output data of his output Jar (Oψ-O ₇₎ in the terminal (Oψ) terminal ₍₁₇ O) signal of a low state one by one sequentially from up to.

However, only four control signals (four CP terminals) are required for the control of the deflop 29, 30, 31 and 32, and the fifth output terminal is required to synchronize with the signal transmission device. When the (O ₄ ) signal is turned low, the high signal through the inverter I ₂ is applied to the terminals MR ₁ and MR ₂ of the counter 27 to reset, so that the count is restarted from the beginning. Therefore, the output of the decoder 28 repeatedly outputs the decoded output by using four units as one unit, and the remaining output terminals Oψ-O ₇ are used at the time of expansion like the decoder 21.

Here, as shown in FIGS. 5 and 6, when the output terminal Oψ signal of the decoder 28 is in the rising edge state, the clock terminal signal CP of the de-flop flop 29 is driven by the clock terminal signal CP. Data from the output terminal Oψ-O ₇ of the serial-to-parallel converter 24 is read into the input terminal Dψ-D ₇ of the de-flip-flop 29 to be input, and a control signal is supplied to the control circuit section 2. . Subsequently, when the output terminals O ₁ , O ₂ , and O ₃ signals of the decoder 28 sequentially rise in the rising edge, similarly, the flip-flops 30, 31, and 32 are sequentially turned on one by one. Only the operation is performed to read and input data from the output terminals Q? -Q ₇ of the serial-to-parallel converter 24 so as to sequentially supply control signals to the control circuit section 2.

As described above, the present invention greatly reduces the number of transmission lines for transmitting the signal states of various switches and call buttons installed inside the cage to the control panel, thereby reducing installation and maintenance costs by enabling installation with only a single transmission line. In addition, since the size of the mobile cable can be reduced to reduce the load, power consumption can be reduced.

Claims (2)

In an elevator apparatus for operating a plurality of floors in a building, latch circuits 14, 15, 16, 17, and parallel circuits are mounted on various switches and buttons 9 provided inside the cage 8. A signal transmission device 13 composed of a serial converter 18, a divider 19, a counter 20, and a repetitor 21 is connected to a normal control circuit unit 2 provided inside the control panel 1. De-flop 29, 30, 31, 32, serial-to-parallel converter 24, divider 25, from the signal transmission control device 13 via a single signal transmission line 12; Elevator signal transmission control device characterized in that it is configured by connecting a signal demodulator (11) consisting of a clock generator (26), a counter (27) and a decoder (28). The elevator apparatus according to claim 1, wherein the signal transmission device (13) and the signal demodulation device (11) are expanded and reduced in accordance with the number of functions of various switches and buttons (9) attached to the inside of the cage (8). Signal transmission control unit.

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