JPS61296819A - Composite switch element circuit - Google Patents

Composite switch element circuit

Info

Publication number
JPS61296819A
JPS61296819A JP60138269A JP13826985A JPS61296819A JP S61296819 A JPS61296819 A JP S61296819A JP 60138269 A JP60138269 A JP 60138269A JP 13826985 A JP13826985 A JP 13826985A JP S61296819 A JPS61296819 A JP S61296819A
Authority
JP
Japan
Prior art keywords
fet
voltage
source
switch element
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60138269A
Other languages
Japanese (ja)
Inventor
Masami Ichijo
一條 正美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60138269A priority Critical patent/JPS61296819A/en
Publication of JPS61296819A publication Critical patent/JPS61296819A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain protection against excess current by supervising the drain- source voltage of the 2nd FET 2 and decreasing the on-signal voltage given to the 1st FET and the 2nd FET when it is discriminated as an abnormal voltage so as to limit the current of a composite switch element. CONSTITUTION:When an on-signal is applied between signal terminals G and S to increase the collector current, the source-drain voltage of the 2nd FET 2 is increased proportional to it. When the source-drain voltage of the 2nd FET 2 exceeds the voltage of a constant voltage diode 5, an additional TR 6 is turned on to decrease the gate-source voltage of the 1st FET. As a result, the 1st FET 1 is about to turn off, but the current of the 2nd FET 2 is decreased and then the source-drain voltage is decreased to turn off the additional TR 6 thereby making the collector current constant.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、バイポーラトランジスタにFET (電界効
果トランジスタ)を組み合せて構成する複合形スイッチ
素子回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite switch element circuit constructed by combining a bipolar transistor and an FET (field effect transistor).

〔従来の技術〕[Conventional technology]

かかる複合形スイッチ素子の回路として第4図に示すよ
うに、主スィッチ素子となるバイポーラトランジスタ3
のベース、コレクタ間に第1のFET1のソース、ドレ
インを接続し、該バイポーラトランジスタ3のエミッタ
側に第2のFET2のドレインを接続し、第1のFET
Iと第2のFET2のゲートとを共通接続し、該バイポ
ーラトランジスタ3のベースと第20FET2のソース
間に定電圧ダイオード4を接続したものがすでに知られ
ている。
As shown in FIG. 4, a circuit of such a composite switch element includes a bipolar transistor 3 which becomes the main switch element.
The source and drain of the first FET 1 are connected between the base and collector of the bipolar transistor 3, and the drain of the second FET 2 is connected to the emitter side of the bipolar transistor 3.
It is already known that I and the gate of the second FET 2 are commonly connected, and a constant voltage diode 4 is connected between the base of the bipolar transistor 3 and the source of the 20th FET 2.

前記複合形スイッチ素子において、ゲートソース端子に
オン信号を与えると第1のFETIと第2のFET2と
が導通し、バイポーラトランジスタ3に順方向のベース
電流が流れて、コレクタ。
In the composite switch element, when an ON signal is applied to the gate-source terminal, the first FETI and the second FET 2 are brought into conduction, and a forward base current flows through the bipolar transistor 3, and the collector current flows through the bipolar transistor 3.

ソース間も導通状態となる。The sources also become conductive.

次にゲートソース端子にオフ信号を与えると第1のFE
TIと第2のFET2がターンオフし、それまでコレフ
タルエミッタ方向に流れていたバイポーラトランジスタ
3のコレクタ電流は行き場を失ってコレクタ〜ベース〜
定電圧ダイオード4の経路へ転流する。
Next, when an off signal is applied to the gate source terminal, the first FE
TI and the second FET 2 turn off, and the collector current of the bipolar transistor 3, which had been flowing in the direction of the core emitter, has nowhere to go and flows from the collector to the base.
The current is commutated to the path of the constant voltage diode 4.

これにより、バイポーラトランジスタ3には、極めて大
きな逆方向ベース電流が流れたことになるので、この後
、短時間でターンオフすることができる。
As a result, an extremely large reverse base current flows through the bipolar transistor 3, so that the bipolar transistor 3 can be turned off in a short period of time.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記のごとき第4図に示す複合形スイッチ素子の出力特
性を第5図に示すが、このスイッチ素子は定格電流に比
較して極めて大きな電流を流し得る特性を有している。
FIG. 5 shows the output characteristics of the composite switching element shown in FIG. 4 as described above, and this switching element has a characteristic that allows a current to flow extremely large compared to the rated current.

その理由は、スイッチ素子としては、コレクタ。The reason is that the switch element is the collector.

ソース間のオン電圧の低いものが望まれ、これに答える
べく第1のFETIに電流容量の余裕の大きいものを使
うことにある。この結果、バイポーラトランジスタ3に
は極めて大きな順方向ベース電流が供給できるものにな
っている。
A low source-to-source on-voltage is desired, and in order to meet this requirement, the first FETI is designed to have a large current capacity margin. As a result, an extremely large forward base current can be supplied to the bipolar transistor 3.

第6図に、該複合形スイッチ素子の回路のインパーク装
置やチョッパ装置における直流短絡事故を等価したもの
を示すが、この種の短絡事故時には、スイッチ素子の端
子電圧は直流電源電圧と等しくなり、この時スイッチ素
子に流れる電流が大きい程、素子は破壊し易くなる。
Figure 6 shows the equivalent of a DC short circuit accident in the impark device or chopper device of the circuit of the composite switch element. In the event of this type of short circuit accident, the terminal voltage of the switch element becomes equal to the DC power supply voltage. At this time, the larger the current flowing through the switch element, the more easily the element is destroyed.

このように、前記第4図に示す複合形スイッチ素子は、
大電流を、電圧信号によって、しかも高速でスイッチン
グできるという大きな長所を有しているが、一方で過電
流破壊し易いという欠点があった。
In this way, the composite switch element shown in FIG.
Although it has the great advantage of being able to switch large currents at high speed using voltage signals, it has the disadvantage of being susceptible to overcurrent damage.

本発明の目的は前記従来例の不都合を解消し、過電流に
対する保護が図かれる複合形スイッチ素子回路を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a composite switch element circuit which eliminates the disadvantages of the conventional example and provides protection against overcurrent.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前記目的を達成するため、第1図に示すように
バイポーラトランジスタ3のベース、コレクタ間に第1
のFETIのソース、ドレインを接続し、該バイポーラ
トランジスタ3のエミッタ側に第2のFET2のドレイ
ンを接続し、第10FETIと第2のFET2のゲート
とを共通接続し、該バイポーラトランジスタ3のベース
と第2のFET2のソース間に定電圧ダイオード4を接
続した複合形スイッチ素子において、第2のFET2の
ドレイン、ソース間電圧を監視し、これが異常電圧であ
ることを判断して第1のFETIと第2のFET2に与
えるオン信号電圧を低下させて複合形スイッチ素子の電
流を制限する保護回路10を付加したことを要旨とする
ものである。
In order to achieve the above-mentioned object, the present invention has a first transistor between the base and collector of the bipolar transistor 3, as shown in FIG.
The source and drain of the 10th FETI are connected, the drain of the second FET 2 is connected to the emitter side of the bipolar transistor 3, the gates of the 10th FETI and the second FET 2 are commonly connected, and the base of the bipolar transistor 3 is connected to the drain of the second FET 2. In a composite switch element in which a constant voltage diode 4 is connected between the sources of the second FET 2, the voltage between the drain and the source of the second FET 2 is monitored, and if it is determined that this is an abnormal voltage, the first FETI is The gist is that a protection circuit 10 is added that reduces the on-signal voltage applied to the second FET 2 and limits the current of the composite switch element.

〔作用〕[Effect]

FETのオン状態は、ソース、ドレイン間が低抵抗にな
ったと考えてよい。したがって、第2のFET2のソー
ス、ドレイン間の電圧は、バイポーラトランジスタ3の
電流と比例関係を有するので、この電圧によって電流値
を正確に知ることができる。そこで、本発明によれば第
2のFET2のソース、ドレイン間の電圧が基準電圧値
を越えた場合に、第1と第2のFETのオン信号レベル
を下げてやれば、バイポーラトランジスタ3には基準電
圧値を越えた場合に、第1と第2のFETのオン信号レ
ベルを下げてやれば、バイポーラトランジスタ3には基
準電圧値によって決まる以上の電流は、流れな(なる。
When the FET is in the on state, it can be considered that the resistance between the source and drain becomes low. Therefore, since the voltage between the source and drain of the second FET 2 has a proportional relationship with the current of the bipolar transistor 3, the current value can be accurately determined from this voltage. Therefore, according to the present invention, when the voltage between the source and drain of the second FET 2 exceeds the reference voltage value, by lowering the on-signal level of the first and second FETs, the bipolar transistor 3 If the on-signal level of the first and second FETs is lowered when the reference voltage value is exceeded, a current exceeding that determined by the reference voltage value does not flow through the bipolar transistor 3.

〔実施例〕〔Example〕

以下、図面について本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明回路の1実施例を示す回路図で、第1図
に示す回路の保護回路10として追加のトランジスタ6
と定電圧ダイオード5とを用いた。
FIG. 2 is a circuit diagram showing one embodiment of the circuit of the present invention, in which an additional transistor 6 is added as a protection circuit 10 of the circuit shown in FIG.
and a constant voltage diode 5 were used.

すなわち、第2のFET2のトレインと追加のトランジ
スタ6のベースの間に定電圧ダイオード5を接続し、追
加のトランジスタ6のエミッタと第2のFET2のソー
ス間に接続し、追加のトランジスタ6のコレクタを第1
のFETIのゲートに接続し、第1と第2のFETI、
2のゲートの間に抵抗7を接続して、第2のFET2の
ゲート。
That is, a constant voltage diode 5 is connected between the train of the second FET 2 and the base of the additional transistor 6, connected between the emitter of the additional transistor 6 and the source of the second FET 2, and connected between the collector of the additional transistor 6. The first
connected to the gates of the first and second FETIs,
A resistor 7 is connected between the gates of the second FET2.

ソース間にオン、オフ信号を加えるようにした。Added on/off signals between sources.

次に動作について説明すると、いま、信号端子G、S間
にオン信号(例えば10v)が印加されているとする。
Next, to explain the operation, it is assumed that an on signal (for example, 10V) is applied between signal terminals G and S.

この状態において、コレクタ電流を増やしていくと、第
20FET2のソース、ドレイン間電圧はこれに比例し
て増加する。
In this state, when the collector current is increased, the voltage between the source and drain of the 20th FET 2 increases in proportion to this.

コレクタ電流が増加して、第2のFET2のソース、ド
レイン間電圧が定電圧ダイオード5の電圧を超えた時点
で、追加のトランジスタ6 (バイポーラトランジスタ
、FET、双方共通用可能)がターンオンして第1のF
ETIのゲート、ソース間電圧を低下させる。
When the collector current increases and the voltage between the source and drain of the second FET 2 exceeds the voltage of the constant voltage diode 5, the additional transistor 6 (bipolar transistor, FET, can be used in common) is turned on. 1 F
Reduce the voltage between the gate and source of ETI.

この結果、第1のFETIはターンオフしようとするが
、第2のFET2の電流が減少してソース、ドレイン間
電圧が減少すれば追加のトランジスタ6はターンオフす
る方向になるという動作によって、コレクタ電流は一定
値にとどまることになる。抵抗7は、追加のトランジス
タ6の導通によって信号源が過電流となるのを防止する
ために挿入されている。
As a result, the first FETI tries to turn off, but if the current in the second FET 2 decreases and the voltage between the source and drain decreases, the additional transistor 6 turns off. It will remain at a constant value. The resistor 7 is inserted to prevent the signal source from overcurrent due to conduction of the additional transistor 6.

第3図に本発明回路の出力特性を示す。FIG. 3 shows the output characteristics of the circuit of the present invention.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明の複合形スイッチ素子回路は、
バイポーラトランジスタのベース、コレクタ間に第1の
FETのソース、ドレインを接続し、該バイポーラトラ
ンジスタのエミッタ側に第2のFETのドレインを接続
し、第1のFETと第2のFETのゲートとを共通接続
し、該バイポーラトランジスタのベースと第2のFET
のソース間に定電圧ダイオードを接続した複合形スイッ
チ素子回路において、直流短絡事故などの場合に、スイ
ッチ素子に流れる過電流が小さく抑えられ、その結果、
過電流保護が容易になるものである。
As described above, the composite switch element circuit of the present invention is
The source and drain of the first FET are connected between the base and collector of the bipolar transistor, the drain of the second FET is connected to the emitter side of the bipolar transistor, and the gates of the first FET and the second FET are connected. commonly connected, the base of the bipolar transistor and the second FET
In a composite switch element circuit in which a constant voltage diode is connected between the sources of
This facilitates overcurrent protection.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の複合形スイッチ素子回路の原理的回路
図、第2図は同上1実施例を示す回路図、第3図は出力
特性を示すグラフ、第4図は従来の複合形スイッチ素子
の回路図、第5図はその出力特性を示すグラフ、第6図
は同上直流短絡時の等価回路図である。 1・・・第1のFET    2・・・第2のFET3
・・・バイポーラトランジスタ 4・・・定電圧ダイオード 5・・・定電圧ダイオード
6・・・トランジスタ   7・・・抵抗10・・・過
電流保護回路 第1図 第3図 第4図
Fig. 1 is a principle circuit diagram of the composite switch element circuit of the present invention, Fig. 2 is a circuit diagram showing one embodiment of the same as above, Fig. 3 is a graph showing output characteristics, and Fig. 4 is a conventional composite switch element circuit. A circuit diagram of the element, FIG. 5 is a graph showing its output characteristics, and FIG. 6 is an equivalent circuit diagram at the time of a DC short circuit. 1...First FET 2...Second FET3
... Bipolar transistor 4 ... Constant voltage diode 5 ... Constant voltage diode 6 ... Transistor 7 ... Resistor 10 ... Overcurrent protection circuit Fig. 1 Fig. 3 Fig. 4

Claims (1)

【特許請求の範囲】[Claims] バイポーラトランジスタのベース、コレクタ間に第1の
FETのソース、ドレインを接続し、該バイポーラトラ
ンジスタのエミッタ側に第2のFETのドレインを接続
し、第1のFETと第2のFETのゲートとを共通接続
し、該バイポーラトランジスタのベースと第2のFET
のソース間に定電圧ダイオードを接続した複合形スイッ
チ素子回路において、第2のFETのドレイン、ソース
間電圧を監視し、これが異常電圧であることを判断して
第1のFETと第2のFETに与えるオン信号電圧を低
下させて複合形スイッチ素子の電流を制限する保護回路
を付加したことを特徴とする複合形スイッチ素子回路。
The source and drain of the first FET are connected between the base and collector of the bipolar transistor, the drain of the second FET is connected to the emitter side of the bipolar transistor, and the gates of the first FET and the second FET are connected. commonly connected, the base of the bipolar transistor and the second FET
In a composite switch element circuit in which a constant voltage diode is connected between the sources of the second FET, the voltage between the drain and source of the second FET is monitored, and upon determining that this is an abnormal voltage, the voltage between the first FET and the second FET is switched off. 1. A composite switch element circuit characterized in that a protection circuit is added to limit the current of the composite switch element by reducing the on-signal voltage applied to the composite switch element.
JP60138269A 1985-06-25 1985-06-25 Composite switch element circuit Pending JPS61296819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60138269A JPS61296819A (en) 1985-06-25 1985-06-25 Composite switch element circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60138269A JPS61296819A (en) 1985-06-25 1985-06-25 Composite switch element circuit

Publications (1)

Publication Number Publication Date
JPS61296819A true JPS61296819A (en) 1986-12-27

Family

ID=15217976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60138269A Pending JPS61296819A (en) 1985-06-25 1985-06-25 Composite switch element circuit

Country Status (1)

Country Link
JP (1) JPS61296819A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01133413A (en) * 1987-11-18 1989-05-25 Mitsubishi Electric Corp Composite semiconductor device
US5006736A (en) * 1989-06-13 1991-04-09 Motorola, Inc. Control circuit for rapid gate discharge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01133413A (en) * 1987-11-18 1989-05-25 Mitsubishi Electric Corp Composite semiconductor device
US5006736A (en) * 1989-06-13 1991-04-09 Motorola, Inc. Control circuit for rapid gate discharge

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