JPH0336450B2 - - Google Patents
Info
- Publication number
- JPH0336450B2 JPH0336450B2 JP58217988A JP21798883A JPH0336450B2 JP H0336450 B2 JPH0336450 B2 JP H0336450B2 JP 58217988 A JP58217988 A JP 58217988A JP 21798883 A JP21798883 A JP 21798883A JP H0336450 B2 JPH0336450 B2 JP H0336450B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- gto
- gate
- zener diode
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000002131 composite material Substances 0.000 claims description 20
- 230000015556 catabolic process Effects 0.000 claims description 14
- 230000005669 field effect Effects 0.000 claims description 10
- 239000008186 active pharmaceutical agent Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 101000800116 Homo sapiens Thy-1 membrane glycoprotein Proteins 0.000 description 1
- 101100449816 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GTO1 gene Proteins 0.000 description 1
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 102100033523 Thy-1 membrane glycoprotein Human genes 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000013641 positive control Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08148—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in composite switches
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、ゲートターンオフサイリスタ「以
下、GTOと略記する）と絶縁ゲート型電界効果
トランジスタ（以下、MOS FETと略記する）
とを直列に接続して構成される複合半導体装置の
過電流保護を目的とした保護回路を有する複合半
導体装置に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as GTO) and an insulated gate field effect transistor (hereinafter abbreviated as MOS FET).
This invention relates to a composite semiconductor device having a protection circuit for the purpose of overcurrent protection of the composite semiconductor device configured by connecting in series.
近年、バイポーラ型スイツチング素子とユニポ
ーラ型スイツチング素子、特にMOS FETとを
組合せた所謂BIMOS複合半導体装置の研究が進
んでいる。この複合半導体装置は高耐圧、大電流
密度、高速、しかも制御電力が非常に小さくて済
む等の特長を有し、特に第１図に示すように、
GTO１にMOS FET２がカスコード接続された
ものの場合にはカソードエミツタが開放されてタ
ーンオフするため、通常のサイリスタの逆方向の
ようにターンオフし、高速かつ動耐圧が高く、ま
たGTO単独の場合と異なり、ターンオフ時の電
流分布が広がるので、破壊耐量が大きくなりその
結果、スナバ回路を不要とする等優れた特長を備
えている。
In recent years, research has been progressing on so-called BIMOS composite semiconductor devices that combine bipolar switching elements and unipolar switching elements, especially MOS FETs. This composite semiconductor device has features such as high breakdown voltage, large current density, high speed, and requires very little control power. In particular, as shown in FIG.
In the case of MOS FET2 connected in cascode to GTO1, the cathode emitter is opened and turned off, so it turns off like the reverse direction of a normal thyristor, and has high speed and dynamic withstand voltage, and is different from the case of GTO alone. Since the current distribution at turn-off is widened, the breakdown resistance is increased, and as a result, it has excellent features such as eliminating the need for a snubber circuit.
ところで、従来、回路中の主スイツチング素子
を過電流から保護するには、かかる回路中に例え
ば過電流を検出するための抵抗器を挿入し、この
抵抗器の両端に発生する電圧を検出し、フオトカ
プラ等の手段によつて電気的に絶縁された信号を
主スイツチング素子の制御回路にフイードバツク
させ、この制御回路からのオン信号を停止し、主
スイツチング素子を通電流から保護していた。 By the way, conventionally, in order to protect the main switching element in a circuit from overcurrent, for example, a resistor for detecting overcurrent is inserted into the circuit, and the voltage generated across this resistor is detected. A signal electrically insulated by means such as a photocoupler is fed back to the control circuit of the main switching element, and the ON signal from this control circuit is stopped, thereby protecting the main switching element from passing current.
（図示省略）
しかしながな、上記の方法では過電流を検出す
る目的のためだけに回路中に専用の抵抗器を挿入
しなければならず、この抵抗器で回路動作には無
関係な電力損失が発生すること、信号の絶縁のた
めにフオトカプラ等の絶縁手段が必要なこと、信
号の増幅回路が必要なこと、応答速度が遅いこと
等の欠点を有する。また大電流の主スイツチング
素子を使用した回路ではカーレントトランス
（Ｃ・Ｔ）を前記の抵抗器の代りに用いる方法も
あるが、このＣ・Ｔは大型かつ高価であり、しか
も高速化することが難しいという難点を有する。(Illustration omitted) However, with the above method, a dedicated resistor must be inserted into the circuit just for the purpose of detecting overcurrent, and this resistor causes power loss that is unrelated to circuit operation. This method has drawbacks such as the occurrence of a signal, the need for an insulating means such as a photocoupler for signal isolation, the need for a signal amplification circuit, and a slow response speed. In addition, in circuits using large current main switching elements, there is a method of using a current transformer (CT) instead of the above-mentioned resistor, but this CT is large and expensive, and it is difficult to increase the speed. The problem is that it is difficult to
本発明は上記の事情に基づきなされたもので、
専用の抵抗器、Ｃ・Ｔ等を用いることなく、主ス
イツチング素子を過電流から保護することができ
る複合半導体装置を提供することを目的とする。
The present invention was made based on the above circumstances, and
It is an object of the present invention to provide a composite semiconductor device that can protect a main switching element from overcurrent without using a dedicated resistor, CT, etc.
本発明は、ゲートターンオフサイリスタGTO
のカソード側に直列に接続された絶縁ゲート型電
界効果トランジスタFET2を有する複合半導体装
置において、前記ゲートターンオフサイリスタ
GTOのゲートと絶縁ゲート型電界効果トランジ
スタFET2のソース間に接続された第１のツエナ
ーダイオードZD1および分圧抵抗器R2，R3の直
列体と、この直列体（ZD1＋（R2＋R3））と並列
にそれぞれ接続された第２のツエナーダイオード
ZD2および抵抗器R4と、前記絶縁ゲート型電界効
果トランジスタFET2のゲート・ソース間に接続
され、かつ、その制御電極が前記分圧抵抗器R2，
R3の接続点に接続されたスイツチング素子
THY1とを有し、前記絶縁ゲート型電界効果トラ
ンジスタFET2のオン電圧VD-Sに、前記ゲートタ
ーンオフサイリスタGTOのゲート・カソード間
電圧VG(GTO)-Kを加えた電圧VG(GTO)-Sと、前記第１
のツエナーダイオードZD1の降伏電圧VZ1と、前
記第２のツエナーダイオードZD2の降伏電圧VZ2
との関係が、VG(GTO)-S＜VZ1＜VZ2となるように構
成した複合半導体装置である。
The present invention is a gate turn-off thyristor GTO
In a composite semiconductor device having an insulated gate field effect transistor FET 2 connected in series to the cathode side of the gate turn-off thyristor,
A series body of the first Zener diode ZD 1 and voltage dividing resistors R 2 and R 3 connected between the gate of the GTO and the source of the insulated gate field effect transistor FET 2 , and this series body (ZD 1 + (R 2 + R 3 )) respectively connected in parallel with the second Zener diode
ZD 2 and resistor R 4 are connected between the gate and source of the insulated gate field effect transistor FET 2 , and the control electrode thereof is connected to the voltage dividing resistor R 2 ,
Switching element connected to the connection point of R 3
THY 1 , and a voltage V G (GTO) that is the sum of the on-voltage V DS of the insulated gate field effect transistor FET 2 and the gate-cathode voltage V G (GTO)-K of the gate turn-off thyristor GTO. -S and the first
The breakdown voltage V Z1 of the Zener diode ZD 1 and the breakdown voltage V Z2 of the second Zener diode ZD 2
This is a composite semiconductor device configured such that the relationship between V G(GTO)-S < V Z1 < V Z2 is satisfied.
以下に本発明の一実施例を図を参照して説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明に係る複合半導体装置の等価回
路図であり、第３図は特にGTOの内部構造を模
式的に示した同じくその等価回路図である。 FIG. 2 is an equivalent circuit diagram of the composite semiconductor device according to the present invention, and FIG. 3 is an equivalent circuit diagram schematically showing the internal structure of the GTO.
これらの図において、鎖線で示す部分が入力信
号のバイパス回路Ｂ・Ｐである。 In these figures, the portions indicated by chain lines are input signal bypass circuits B and P.
すなわち、制御入力端子Ｇ−Ｓ間にサイリスタ
THY1を設け、このサイリスタTHY1の制御極
を、ツエナーダイオードZD1のアノード側に接続
したり分圧抵抗器R2，R3との接続点に接続し、
ツエナーダイオードZD1のカソード側と、抵抗器
R3の一端が接続された制御入力端子Ｓとの間に
は、図示のようにツエナーダイオードZD2及び抵
抗器R4とを並列に接続してある。 In other words, a thyristor is connected between the control input terminals G and S.
THY 1 is provided, and the control pole of this thyristor THY 1 is connected to the anode side of Zener diode ZD 1 or to the connection point with voltage dividing resistors R 2 and R 3 ,
Cathode side of Zener diode ZD 1 and resistor
As shown in the figure, a Zener diode ZD 2 and a resistor R 4 are connected in parallel between the control input terminal S to which one end of R 3 is connected.
尚、図中、R1はMOS FET1、MOS FET2の
ノイズ耐量を改善するための抵抗器であつて、本
発明の要旨とは直接関係しない。また、ツエナー
ダイオードZD1の降伏電圧VZ1は常にツエナーダ
イオードZD2の降伏電圧VZ2よりも低く、定常動
作状態におけるMOS FET2のオン電圧VD-Sより
も高い値に選ばれている。 In the figure, R 1 is a resistor for improving the noise resistance of MOS FET 1 and MOS FET 2 , and is not directly related to the gist of the present invention. Furthermore, the breakdown voltage V Z1 of the Zener diode ZD 1 is always lower than the breakdown voltage V Z2 of the Zener diode ZD 2 and is selected to be higher than the on-voltage V DS of the MOS FET 2 in the steady operating state.
すなわち、VD-S＜VZ1＜VZ2の関係にある。 That is, the relationship is V DS <V Z1 <V Z2 .
上記の回路において抵抗器R4は正常動作時に
MOS FET1及びMOS FET2の各ゲートＧに制御
入力端子Ｇからの入力信号VSig.が印加されるよう
にするためのものであり、GTOの順阻止接合J2
のもれ電流がゲートを介してこの抵抗器R4に流
れた時にその電圧降下が十分に低い値、すなわ
ち、ツエナーダイオードZD1の降伏電圧VZ1以下
になるように選定しておく。 In the above circuit, resistor R 4 is
This is to apply the input signal V Sig. from the control input terminal G to each gate G of MOS FET 1 and MOS FET 2 , and the forward blocking junction J 2 of GTO
The resistor is selected so that when the leakage current flows through the gate to this resistor R4 , the voltage drop will be a sufficiently low value, that is, below the breakdown voltage VZ1 of the Zener diode ZD1 .
なお、この抵抗器R4が無い場合は次のような
不都合が生じる。すなわち、上記の複合半導体装
置がオフ状態にある場合には、電源電圧Ｅが
GTOの順阻止接合J2で殆んど分担され残余の電
圧はツエナーダイオードZD2の降伏電圧VZ2で制
限される電圧の範囲内でMOS FET2が分担する
こととなる。したがつてGTOの順阻止接合J2の
もれ電流がMOS FET2のもれ電流よりも大きい
と、このFET2にはツエナーダイオードZD2の降
伏電圧VZ2からGTOのゲート・カソード間電圧
VG(GTO)-Kを引いた電圧、すなわちVZ2−
（VG(GTO)-K）の電圧がかかる。これにより、GTO
の順阻止接合J2のゲートを介してもれ電流がツエ
ナーダイオードZD1→抵抗器R2→抵抗器R3を経
て分流し、抵抗器R3の両端の電圧降下がTHY1
のゲートトリガ電圧VGTを越えると、THY1にゲ
ート電流が流れ、このTHY1がターンオフし、制
御入力端子Ｇ−Ｓ間を短絡してしまう。その結
果、制御入力信号VSig.がMOS FET1及びMOS
FET2のゲートＧに加わらず、この複合半導体装
置をターンオンされることができなくなつてしま
う。 Note that if this resistor R4 is not provided, the following inconvenience will occur. That is, when the above composite semiconductor device is in the off state, the power supply voltage E is
Most of the voltage is shared by the forward blocking junction J2 of the GTO, and the remaining voltage is shared by the MOS FET 2 within the voltage range limited by the breakdown voltage VZ2 of the Zener diode ZD2. Therefore, if the leakage current of the forward blocking junction J 2 of the GTO is larger than the leakage current of MOS FET 2 , this FET 2 has a voltage between the gate and cathode of the GTO from the breakdown voltage V Z2 of the Zener diode ZD 2 .
The voltage minus V G(GTO)-K , that is, V Z2 −
A voltage of (V G(GTO)-K ) is applied. This allows G.T.O.
The leakage current is shunted through the gate of the forward blocking junction J 2 through the Zener diode ZD 1 → resistor R 2 → resistor R 3 , and the voltage drop across the resistor R 3 becomes THY 1
When the gate trigger voltage V GT is exceeded, a gate current flows through THY 1 , turning off THY 1 and shorting the control input terminals GS and GS. As a result, the control input signal V Sig .
It does not apply to the gate G of FET 2 , making it impossible to turn on this composite semiconductor device.
そこで、図示のように抵抗器R4を設け、複合
半導体装置の正常動作時には前記入力信号VSig.が
MOS FET1及びMOS FET2の各ゲートＧに確実
に印加されるように構成したものである。 Therefore, a resistor R4 is provided as shown in the figure, so that during normal operation of the composite semiconductor device, the input signal V Sig.
The configuration is such that the voltage is reliably applied to each gate G of MOS FET 1 and MOS FET 2 .
すなわち、制御入力端子Ｇ−Ｓに正の入力信号
VSig.が印加されると、先ずMOS FET2がターン
オンし、次いでMOS FET1がターンオンする。
これによりGTOのゲートＧに正のゲート電流が
供給されこのGTOがターンオンする。その後、
アノード電流iA（同一値を持つMOS FET2のドレ
イン電流iDが次第に増加して行き、予め定められ
た基準値IREF.に到達する。ここで、MOS FET2
はオン状態において抵抗特性を持つため、この
FET2のオン電圧VD-Sは前記FET2のドレイン電
流iDに比例して増加する。 That is, a positive input signal is applied to the control input terminal G-S.
When V Sig. is applied, MOS FET 2 is turned on first, and then MOS FET 1 is turned on.
As a result, a positive gate current is supplied to the gate G of the GTO, turning the GTO on. after that,
Anode current i A (drain current i D of MOS FET 2 having the same value gradually increases and reaches a predetermined reference value I REF . Here, MOS FET 2
has resistance characteristics in the on state, so this
The on-voltage V DS of FET 2 increases in proportion to the drain current i D of FET 2 .
上記の状態を第４図に示す。 The above state is shown in FIG.
同図は横軸に時間、縦軸に電流及び電圧をそれ
ぞれ示し、またiAを前記アノード電流、iDを前記
ドレイン電流、IREF.を基準値、VD-Sを前記FET2
のオン電圧、VG(GTO)-KをGTOのゲート・カソー
ド間電圧、VG(GTO)-SをGTOのゲート端子とMOS
FET2のソース端子間に発生する電圧、VREF.を概
略ツエナーダイオードZD1の降伏電圧VZ1とサイ
リスタTHY1のゲートトリガ電流VGT(THY1)との和
で決る基準電圧、VZ2をツエナーダイオードZD2
の降伏電圧をそれぞれ示す。 In the figure, the horizontal axis shows time, and the vertical axis shows current and voltage, and i A is the anode current, i D is the drain current, I REF. is the reference value, and V DS is the FET 2.
, V G(GTO)-K is the gate-cathode voltage of GTO, and V G(GTO)-S is the voltage between GTO gate terminal and MOS.
The voltage generated between the source terminals of FET 2, V REF. , is the reference voltage determined by the sum of the breakdown voltage V Z1 of the Zener diode ZD 1 and the gate trigger current V GT (THY1) of the thyristor THY 1 , and V Z2 is the Zener diode ZD. Diode ZD 2
The breakdown voltage of each is shown.
上記の図から明らかなように時間t0でMOS
FET2がオン状態となり、その後オン電圧VD-Sが
ドレイン電流iDに比例して増加して行き、GTO
のゲート端子とMOS FET2のソース端子の間に
発生する電圧はMOS FET2のオン電圧VD-S(〓)に
GTOのゲート・カソード間電圧VG(GTO)-K(〓)を加え
た図示のVG(GTO)-S(〓)で示す直線となる。 As is clear from the above figure, at time t 0 MOS
FET 2 turns on, and then the on-voltage V DS increases in proportion to the drain current i D , and the GTO
The voltage generated between the gate terminal of MOS FET 2 and the source terminal of MOS FET 2 is equal to the on-voltage V DS (
The GTO gate-to-cathode voltage V G(GTO)-K( 〓 ) is added to the straight line shown by V G(GTO)-S( 〓 ) in the figure.
今、GTOのアノード電流iA（MOS FET2のド
レイン電流iD）が増加することによつて前記
VG(GTO)-S(〓)がVREF.以上に増加すると、ツエナーダ
イオードZD1の降伏電圧VZ1に達し電流がツエナ
ーダイオードZD1→抵抗器R2→抵抗器R3と流れ
る。その結果この抵抗器R3の両端の電圧降下が
サイリスタTHY1のゲートトリガ電流VGT以上の
値にあると、このサイリスタTHY1がターンオン
し、MOS FET1及びMOS FET2のゲート電位を
各々のスレツシユホールド電圧Vth以下の値にク
ランプする。 Now, by increasing the anode current i A of GTO (drain current i D of MOS FET 2 ), the above
When V G(GTO)-S( 〓 ) increases above V REF. , the breakdown voltage V Z1 of the Zener diode ZD 1 is reached and current flows from the Zener diode ZD 1 → resistor R 2 → resistor R 3 . As a result, if the voltage drop across this resistor R 3 is greater than or equal to the gate trigger current V GT of thyristor THY 1 , this thyristor THY 1 turns on and changes the gate potentials of MOS FET 1 and MOS FET 2 to their respective Clamp to a value below the threshold voltage V th .
この結果、MOS FET1及びMOS FET2がター
ンオフする。一方、GTOのアノード電流iAは
MOS FET2から該GTOのゲートを介してツエナ
ーダイオードZD2へと転流する。その後、この複
合半導体装置はエミツタ開放によりサイリスタの
逆方向の如くターンオンするのでこの半導体装置
は過電流によつて破壊されることから効果的に保
護されることになる。 As a result, MOS FET 1 and MOS FET 2 are turned off. On the other hand, the anode current i A of GTO is
The current is commutated from the MOS FET 2 to the Zener diode ZD 2 via the gate of the GTO. Thereafter, this composite semiconductor device is turned on like a thyristor in the opposite direction by opening its emitter, so that this semiconductor device is effectively protected from being destroyed by overcurrent.
また、上記の回路においてサイリスタTHY1は
自己保持機能を有するため、制御入力信号VSig.が
引き続き正の状態にあつても、MOS FET1及び
MOS FET2には正の信号が印加されることがな
い。一方、制御入力信号VSig.が負の状態若しくは
零になつてサイリスタTHY1のターンオフ時間で
決るある一定時間以上経過した後に、再度、正の
制御入力端子VSig.が入力された時のみこの複合半
導体装置が再点弧する。 In addition, in the above circuit, thyristor THY 1 has a self-holding function, so even if the control input signal V Sig. continues to be in a positive state, MOS FET 1 and
No positive signal is applied to MOS FET 2 . On the other hand, only when the positive control input terminal V Sig. is input again after the control input signal V Sig. becomes negative or zero and a certain period of time determined by the turn-off time of thyristor THY 1 has elapsed. The composite semiconductor device is re-ignited.
また、MOS FETのオン抵抗値は正の温度特
性を持つため、MOS FET2の接合温度が上昇す
る程、過電流検出値IREF.が下がり、複合半導体装
置をより安全に保護できるようになる。 In addition, since the on-resistance value of MOS FET has a positive temperature characteristic, as the junction temperature of MOS FET 2 rises, the overcurrent detection value I REF. decreases, making it possible to more safely protect the composite semiconductor device. .
上記したように本発明では複合半導体装置を構
成するGTOに直列接続したMOS FETのオン抵
抗特性を過電流検出に利用しており、従来のよう
に装置外部に過電流検出専用の抵抗器を設ける必
要がなく、また過電流検出信号をフオトカプラの
ような電気的絶縁手段を介して制御回路に送り、
オン信号を遮断するというような構成が不要であ
つて制御入力信号を直接、インターロツクして保
護することが可能である。さらに上記の過電流保
護機能を有する回路を１つの複合半導体装置のパ
ツケージ内に組み込むことにより、自己保護機能
を備えたコンパクトかつ使用し易い複合半導体装
置となる。
As mentioned above, in the present invention, the on-resistance characteristic of the MOS FET connected in series with the GTO that constitutes the composite semiconductor device is used for overcurrent detection, and unlike the conventional device, a resistor dedicated to overcurrent detection is provided outside the device. There is no need to send the overcurrent detection signal to the control circuit via electrical isolation means such as a photocoupler.
It is possible to directly interlock and protect the control input signal without requiring any configuration to block the on signal. Furthermore, by incorporating the circuit having the above-mentioned overcurrent protection function into a single composite semiconductor device package, a compact and easy-to-use composite semiconductor device having a self-protection function can be obtained.
第１図は従来の複合半導体装置の一例を示す回
路図、第２図は本発明の一実施例を示す複合半導
体装置の回路図、第３図は同じくその等価回路
図、第４図は上記複合半導体装置のターンオン時
の各部の電流、電圧関係を示す図である。
GTO……ゲート・ターン・オフサイリスタ、
FET1，FET2……絶縁ゲート型電界効果トラン
ジスタ、ZD1，ZD2……ツエナーダイオード、
THY1……サイリスタ、R1，R2，R3，R4……抵
抗。
Fig. 1 is a circuit diagram showing an example of a conventional composite semiconductor device, Fig. 2 is a circuit diagram of a complex semiconductor device showing an embodiment of the present invention, Fig. 3 is an equivalent circuit diagram thereof, and Fig. 4 is the above-mentioned circuit diagram. FIG. 3 is a diagram showing the current and voltage relationships of various parts when the composite semiconductor device is turned on. GTO...Gate turn off thyristor,
FET 1 , FET 2 ... Insulated gate field effect transistor, ZD 1 , ZD 2 ... Zener diode,
THY 1 ...Thyristor, R1 , R2 , R3 , R4 ...Resistor.
Claims (1)
ド側に直列に接続された絶縁ゲート型電界効果ト
ランジスタFET2を有する複合半導体装置におい
て、 前記ゲートターンオフサイリスタGTOのゲー
トと絶縁ゲート型電界効果トランジスタFET2の
ソース間に接続された第１のツエナーダイオード
ZD1および分圧抵抗器R2，R3の直列体と、この
直列体（ZD1＋（R2＋R3））と並列にそれぞれ接
続された第２のツエナーダイオードZD2および抵
抗器R4と、前記絶縁ゲート型電界効果トランジ
スタFET2のゲート・ソース間に接続され、か
つ、その制御電極が前記分圧抵抗器R2，R3の接
続点に接続されたスイツチング素子THY1とを有
し、 前記絶縁ゲート型電界効果トランジスタFET2
のオン電圧VD-Sに、前記ゲートターンオフサイ
リスタGTOのゲート・カソード間電圧VG(GTO)-K
を加えた電圧VG(GTO)-Sと、前記第１のツエナーダ
イオードZD1の降伏電圧VZ1と、前記第２のツエ
ナーダイオードZD2の降伏電圧VZ2との関係が、 VG(GTO)-S＜VZ1＜VZ2となるように構成したこと
を特徴とする複合半導体装置。[Scope of Claims] 1. A composite semiconductor device including an insulated gate field effect transistor FET 2 connected in series to the cathode side of a gate turn-off thyristor GTO, comprising the gate of the gate turn-off thyristor GTO and the insulated gate field effect transistor FET. The first Zener diode connected between the sources of 2
A series body of ZD 1 and voltage dividing resistors R 2 and R 3 , and a second Zener diode ZD 2 and resistor R 4 connected in parallel with this series body (ZD 1 + (R 2 + R 3 )), respectively . and a switching element THY 1 connected between the gate and source of the insulated gate field effect transistor FET 2 , and whose control electrode is connected to the connection point of the voltage dividing resistors R 2 and R 3 . and the insulated gate field effect transistor FET 2
The on-voltage V DS of the gate turn-off thyristor GTO and the gate-cathode voltage V G(GTO)-K
The relationship between the voltage V G(GTO)-S , the breakdown voltage V Z1 of the first Zener diode ZD 1 , and the breakdown voltage V Z2 of the second Zener diode ZD 2 is V G(GTO )-S < V Z1 < V Z2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58217988A JPS60109919A (en) | 1983-11-18 | 1983-11-18 | Composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58217988A JPS60109919A (en) | 1983-11-18 | 1983-11-18 | Composite semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60109919A JPS60109919A (en) | 1985-06-15 |
| JPH0336450B2 true JPH0336450B2 (en) | 1991-05-31 |
Family
ID=16712856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58217988A Granted JPS60109919A (en) | 1983-11-18 | 1983-11-18 | Composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60109919A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153222A (en) * | 1984-01-20 | 1985-08-12 | Miki Puurii Kk | Switching circuit |
| FR2611098B1 (en) * | 1987-02-13 | 1989-06-09 | Telemecanique Electrique | SERIAL MOUNT POWER SWITCH COMPRISING A GTO THYRISTOR AND A MOS FIELD EFFECT TRANSISTOR |
| FR2613889B1 (en) * | 1987-04-07 | 1990-11-16 | Telemecanique Electrique | CONTROL STAGE OF A STATIC POWER SWITCH WITH CONTROLLABLE LOCK |
| JP2506434Y2 (en) * | 1991-11-01 | 1996-08-07 | 株式会社神戸製鋼所 | Extruder die head |
-
1983
- 1983-11-18 JP JP58217988A patent/JPS60109919A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60109919A (en) | 1985-06-15 |
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