JPS6129553U - wireless communication device - Google Patents
wireless communication deviceInfo
- Publication number
- JPS6129553U JPS6129553U JP11315184U JP11315184U JPS6129553U JP S6129553 U JPS6129553 U JP S6129553U JP 11315184 U JP11315184 U JP 11315184U JP 11315184 U JP11315184 U JP 11315184U JP S6129553 U JPS6129553 U JP S6129553U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- pulse train
- circuit
- communication device
- wireless communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Selective Calling Equipment (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例の回路構成図、第２図は同上の
アンテナを共通に使用する場合の要部の回路構成図、第
３図は同上の要部の動作説明図、第４図及び第５図はそ
れぞれ同上の動作説明図である。
２はパルス列発生回路、３はオア回路、４は変調回路、
５は発振回路、６は復調回路、７はオア回路、８はパル
ス解読回路、９は送信器、１０は受信器である。Fig. 1 is a circuit configuration diagram of an embodiment of the present invention, Fig. 2 is a circuit configuration diagram of the main part when the above antenna is used in common, Fig. 3 is an explanatory diagram of the operation of the main part of the above, and Fig. 4 5 and 5 are explanatory diagrams of the same operation as above, respectively. 2 is a pulse train generation circuit, 3 is an OR circuit, 4 is a modulation circuit,
5 is an oscillation circuit, 6 is a demodulation circuit, 7 is an OR circuit, 8 is a pulse decoding circuit, 9 is a transmitter, and 10 is a receiver.
Claims (1)
パルス数等で互いに異なる形のパルス列からなる２個の
パルス列信号を時系列的に１ブロックとして出力するパ
ルス列発生回路と、パルス列発生回路からの出力パルス
列信号を異なる周波数の搬送波で送信する送信手段とを
備えると共に、相手局からの各周波数の搬送波を各別に
受信復調する受信手段と、復調されたパルス列信号の論
理和をとるオア回路と、該オア回路の出力パルス列信号
から相手局の入カパルスを再生するパルス解読回路とを
備えて成ることを特徴とするワイヤレス通信機。Corresponding to the rising and falling edges of the input pulse, the pulse width,
A pulse train generation circuit that outputs two pulse train signals consisting of pulse trains of different shapes in terms of the number of pulses etc. as one block in time series, and a transmission means that transmits the output pulse train signals from the pulse train generation circuit using carrier waves of different frequencies. and a receiving means for separately receiving and demodulating the carrier waves of each frequency from the partner station, an OR circuit for ORing the demodulated pulse train signals, and an input pulse of the partner station from the output pulse train signal of the OR circuit. What is claimed is: 1. A wireless communication device comprising: a regenerating pulse decoding circuit;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11315184U JPS6129553U (en) | 1984-07-25 | 1984-07-25 | wireless communication device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11315184U JPS6129553U (en) | 1984-07-25 | 1984-07-25 | wireless communication device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6129553U true JPS6129553U (en) | 1986-02-22 |
Family
ID=30672184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11315184U Pending JPS6129553U (en) | 1984-07-25 | 1984-07-25 | wireless communication device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6129553U (en) |
-
1984
- 1984-07-25 JP JP11315184U patent/JPS6129553U/en active Pending
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