JPS61292351A - Input protecting circuit - Google Patents

Input protecting circuit

Info

Publication number
JPS61292351A
JPS61292351A JP13474985A JP13474985A JPS61292351A JP S61292351 A JPS61292351 A JP S61292351A JP 13474985 A JP13474985 A JP 13474985A JP 13474985 A JP13474985 A JP 13474985A JP S61292351 A JPS61292351 A JP S61292351A
Authority
JP
Japan
Prior art keywords
input
source
transistor
drain
breakdown voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13474985A
Other languages
Japanese (ja)
Inventor
Toshio Wada
和田　俊男
Takashi Takesono
竹園　隆
Takashi Okada
敬 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP13474985A priority Critical patent/JPS61292351A/en
Publication of JPS61292351A publication Critical patent/JPS61292351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To apply an input surge voltage to a ground by uniformly distributing it by varying a breakdown voltage between a source and a drain by altering a polysilicon resistor and a channel length in combination with a protecting MIS transistor for varying the breakdown voltage between the source and the drain. CONSTITUTION:An input protecting circuit has an input pad 1 formed of aluminum, a polysilicon resistor 2 made of an N<+> type polysilicon layer formed on the field insulating film of a semiconductor substrate 3, and a protecting MIS transistor 4. The transistor 4 is formed by separating source and drain regions 5, 6 made of N<+> type diffused layers, a step 8 is formed on the portion of the region 6 opposed to a channel region 7, and channel length L is varied to L1, L2, L3, L4. THe channel length L of the transistor is gradually reduced to gradually decrease a breakdown voltage BVDS between the source and the drain. Accordingly, an input surge voltage can be uniformly dispersed in the channel of the transistor. A large input surge voltage is applied to a ground at the side connected with the resistor 2, and a small input surge voltage is applied to the ground at the gate electrode side.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明はＭＩＳトランジスタ回路の入力保護回路の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in input protection circuits for MIS transistor circuits.

（０）従来の技術 従来の入力保護回路としては第４図に示す拡散抵抗を用
いるものが例えば特公昭４５−３４６４１号公報等で知
られている。(0) Prior Art As a conventional input protection circuit, one using a diffused resistor as shown in FIG. 4 is known, for example, from Japanese Patent Publication No. 45-34641.

第４図に於て、（２１）はＡｆｆｉ　により形成された
入力パッド、（２２）は半導体基板に不純物を拡散して
形成きれた拡散抵抗であり、パターン的には入力バット
（２１）から拡散抵抗（２２）の一端にコンタクトを介
して入り、拡散抵抗（２２）の他端よりコンタクトを介
してＡｌ　　配線（２３）で保護されるＭＩＳトランジ
スタのゲート電極に接続きれている。第５図は第４図の
入力保護回路の等価回路図であり、拡散抵抗（２２）は
抵抗と同時に基板との間で逆方向のダイオードを形成し
ており、抵抗で形成される時定数回路で入力サージ電圧
をなめすと同時にダイオードで基板へ抜いてＭＩＳトラ
ンジスタのゲート酸化膜を破壊されるのを防止している
。In Fig. 4, (21) is an input pad formed by Affi, and (22) is a diffused resistor formed by diffusing impurities into the semiconductor substrate. It enters one end of the resistor (22) via a contact, and is connected to the gate electrode of a MIS transistor protected by an Al wiring (23) from the other end of the diffused resistor (22) via the contact. Figure 5 is an equivalent circuit diagram of the input protection circuit in Figure 4, where the diffused resistor (22) forms a diode in the opposite direction between the resistor and the substrate, and a time constant circuit formed by the resistor. At the same time, the diode drains the input surge voltage to the substrate to prevent the gate oxide film of the MIS transistor from being destroyed.

従来の他の入力保護回路としては第６図に示すポリシリ
コン抵抗を用いるものが例えば特開昭５９−７４６６５
号公報等で知られている。Another conventional input protection circuit using a polysilicon resistor as shown in FIG.
It is known from the publication No.

第６図に於て、　（３１）はＡＪ２　　により形成きれ
た入力パッド、（３２）は半導体基板の絶縁膜上に形成
きれたＮ＋ポリシリコン層より成るポリシリコン抵抗体
であり、パターン的には入力バッド（３１）からポリシ
リコン抵抗体（３２）の一端にコンタクトを介して入り
、ポリシリコン抵抗体（３２）の他端よりコンタクトを
介してＡ！　配線（３３）で保護キれるＭＩＳトランジ
スタのゲート電極に接続されている。In Fig. 6, (31) is an input pad completely formed by AJ2, and (32) is a polysilicon resistor made of an N+ polysilicon layer completely formed on an insulating film of a semiconductor substrate. The input pad (31) enters one end of the polysilicon resistor (32) via a contact, and the A! It is connected to the gate electrode of the MIS transistor, which can be protected by a wiring (33).

第７図は第６図の入力保護回路の等価回路図であり、ポ
リシリコン抵抗体（３２）とポリシリコン抵抗体（３２
）下のＭＯ３容量とで形成される時定数回路で入力サー
ジ電圧をなめしてＭＩＳトランジスタのゲートｍ化膜を
保護している。FIG. 7 is an equivalent circuit diagram of the input protection circuit shown in FIG.
) The time constant circuit formed by the MO3 capacitor below smoothes the input surge voltage and protects the gate m-oxide film of the MIS transistor.

（ハ）発明が解決しようとする問題点 前者の従来の入力保護回路では大きい入力サージ電圧が
印加されると拡散抵抗（２２）の入力パッド（２１）側
に集中して加えられるので入力バッド側のＰＮ接合が破
壊され易い欠点がある。(c) Problems to be solved by the invention In the former conventional input protection circuit, when a large input surge voltage is applied, it is concentrated on the input pad (21) side of the diffused resistor (22), so the input pad side The disadvantage is that the PN junction is easily destroyed.

後者の従来の入力保護回路では大きい入力サージ電圧が
印加されると入力サージ電圧は基板に抜く構造となって
いないので、ポリシリコン抵抗（３２）を介してＭＩＳ
トランジスタのゲート電極に印加きれてゲート酸化膜を
破壊してしまう欠点がある。In the latter conventional input protection circuit, when a large input surge voltage is applied, the input surge voltage is not connected to the MIS via the polysilicon resistor (32) because it is not designed to be extracted to the board.
The drawback is that the voltage cannot be applied to the gate electrode of the transistor, destroying the gate oxide film.

輛）問題点を解決するための手段 本発明は衛士した欠点に鑑みてな許れ、ポリシリコン抵
抗体（２）とチャンネル長を変化させてソースドレイン
間ブレークダウン電圧を変化させた保護用ＭＩＳトラン
ジスタ（４）との組み合せにより従来の欠点を大巾に改
善した入力保護回路を実現するものである。輛) Means for Solving the Problems In view of the drawbacks of the present invention, the present invention is a protective MIS in which the source-drain breakdown voltage is changed by changing the polysilicon resistor (2) and the channel length. In combination with the transistor (4), an input protection circuit is realized which greatly improves the conventional drawbacks.

（＊）作用 本発明に依れば、ポリシリコン抵抗体（２）で入力サー
ジ電圧をなめした後、保護用ＭＩＳトランジス（４）で
入力サージ電圧をソースドレイン間ブレークダウン電圧
を変化させて均一に分布きせてグランドに抜いているの
で大きい入力サージ電圧でも入力保護回路を破壊するこ
となく保護できる。(*) Effect According to the present invention, after the input surge voltage is smoothed by the polysilicon resistor (2), the input surge voltage is uniformed by changing the source-drain breakdown voltage by the protective MIS transistor (4). The input protection circuit can be protected without destroying the input protection circuit even with large input surge voltage because it is distributed over the ground and connected to the ground.

（へ）実施例 本発明に依る入力保護回路を第１図乃至第３図を参照し
て詳述する。(F) Embodiment The input protection circuit according to the present invention will be described in detail with reference to FIGS. 1 to 3.

第１図は本発明の入力保護回路の上面図を示し、（１）
は八〇　　により形成された入力バット、（２〉は半導
体基板（３）のフィールド絶縁膜上に形成きれたＮ＋ポ
リシリコン層より成るポリシリコン抵抗体、（４）は本
発明の特徴とする保護用ＭＩＳトランジスタである。こ
の保護用ＭＩＳトランジスタ（４）は点線で示すＮ＋型
型数散層り成るソースドレイン領域（５）（６）が離間
して設けられ、ドレイン領域（６）にチャンネル領域（
７）と対抗している部分にステップ（８）を形成してい
る。このステップ（８）はチャンネル領域（７）のほぼ
金山に渡って形成きれ、チャンネル長りをり、、Ｌ、、
Ｌ、、Ｌ４と可変している。即ちチャンネル長りはポリ
シリコン抵抗（２）に接続きれた側から保護されるＭＩ
Ｓトランジスタのゲート電極側に行くに従いその長さを
漸減させている。FIG. 1 shows a top view of the input protection circuit of the present invention, (1)
(2) is a polysilicon resistor made of an N+ polysilicon layer completely formed on the field insulating film of the semiconductor substrate (3), and (4) is the protection characteristic of the present invention. This protection MIS transistor (4) is provided with source and drain regions (5) and (6) separated from each other, each consisting of an N+ type scattering layer shown by a dotted line, and a channel region in the drain region (6). (
A step (8) is formed in the portion opposite to step (7). This step (8) is completely formed over almost the entire length of the channel region (7), and the channel length is .
It is variable as L, , L4. In other words, the channel length is protected from the side connected to the polysilicon resistor (2).
The length is gradually reduced toward the gate electrode side of the S transistor.

パターン的には、入カパツドク１）はポリシリコン抵抗
体（２）の一端にコンタクトを介して接続きれている。In terms of pattern, the input capacitor 1) is connected to one end of the polysilicon resistor (2) via a contact.

ポリシリコン抵抗体（２）の他端からはフンタクトを介
して保護用ＭＩＳＩ−ランジスタ（４）のドレイン領域
（６）の一端までＡＮ　配線で接続きれ、保護用ＭＩＳ
トランジスタ（４）のゲート電極（９）はチャンネル領
域（７）上のゲート酸化膜を被覆し且つソース領域（５
）にコンタクトを介して接続きれ、更にグランドまたは
電源に導かれている。また保護されるＭＩＳトランジス
タのゲート電極（１０）はドレイン領域（６）の他端に
コンタクトを介して接続されている。The other end of the polysilicon resistor (2) can be connected to one end of the drain region (6) of the protective MISI resistor (4) via a contact with AN wiring, and the protective MISI
The gate electrode (9) of the transistor (4) covers the gate oxide film on the channel region (7) and covers the source region (5).
) via a contact, and is further led to ground or power supply. Further, the gate electrode (10) of the MIS transistor to be protected is connected to the other end of the drain region (6) via a contact.

第２図は第１図の本発明の等価回路図であり、ポリシリ
コン抵抗体（２）とチャンネル長りを変えてソースドレ
イン間ブレークダウン電圧の異なる複数の保護用ＭＩＳ
トランジスタ（４）とを介して入力バッド（１）と保護
されるＭＩＳ）−ランジスタのゲート電極とを接続して
いる。この複数個の保護用ＭＩＳトランジスタはポリシ
リコン抵抗体（２）側よりチャンネル長りが漸減され、
ソースドレイン間ブレークダウン電圧ＶＴは漸減する様
に設定きれ、入力サージ電圧を各保護用ＭＩＳトランジ
スタに平均的に分散きせている。FIG. 2 is an equivalent circuit diagram of the present invention shown in FIG. 1, and shows a plurality of protective MISs having different source-drain breakdown voltages by changing the polysilicon resistor (2) and channel length.
The input pad (1) and the gate electrode of the protected MIS transistor are connected via the transistor (4). The channel length of these multiple protective MIS transistors is gradually decreased from the polysilicon resistor (2) side.
The source-drain breakdown voltage VT can be set to gradually decrease, and the input surge voltage is evenly distributed to each protective MIS transistor.

本発明による入力保護回路の動作について説明する。保
護用ＭＩＳトランジスタは前述した如くチャンネル長り
がＬｌ、Ｌ２、Ｌ８、Ｌ４と漸減する様に設計きれてい
る。例えばチャンネル長をり、＝７μｍ、Ｌ！−３μｍ
、Ｌｓ＝２１１ｍ、Ｌ４＝１．５μｍと漸減きせると、
第３図よりソースドレイン間ブレークダウン電圧ＢＶｏ
ｓは２１Ｖ、１７Ｖ、１４Ｖ、１２Ｖと変化する。なお
第３図では１００国のＰ型シリコン基板のフィールド表
面不純物、濃度を２×１０　”Ｃｒ１ｌ−”とし、ゲー
ト酸化膜厚ｔ　ａｔ、４００人、ソースドレイン領域の
拡散深さｘｊを０．５μｍとした保護用ＭＩＳトランジ
スタを例に採った。一方保護されるＭＩＳトランジスタ
の保護ゲート耐圧を約１５Ｖとして設計している。The operation of the input protection circuit according to the present invention will be explained. As described above, the protection MIS transistor is designed so that the channel length gradually decreases from Ll, L2, L8, and L4. For example, channel length = 7 μm, L! -3μm
, Ls=211m, L4=1.5μm and gradually decrease,
From Figure 3, source-drain breakdown voltage BVo
s changes to 21V, 17V, 14V, and 12V. In Fig. 3, the field surface impurity concentration of a P-type silicon substrate from 100 countries is 2 x 10 "Cr1l-", the gate oxide film thickness t is 400, and the diffusion depth xj of the source and drain regions is 0.5 μm. We took a protection MIS transistor as an example. On the other hand, the protection gate breakdown voltage of the MIS transistor to be protected is designed to be approximately 15V.

斯る入力保護回路では大きい入力サージ電圧は大きいソ
ースドレイン間ブレークダウン電圧ＢＶ□を有するポリ
シリコン抵抗体（２〉に接続きれた側でグランドに抜く
ことができ、小さい入力サージ電圧は小さいソースドレ
イン間ブレークダウン電圧ＢＶＤＳを有するゲート電極
側でグランドに抜くことができ；入力サージ電圧をソー
スドレイン間ブレークダウン重圧ＢＶＤＳの大きさによ
り保護用ＭＩＳトランジスタに均一に分散できる。これ
から保護用ＭＩＳトランジスタのソースドレイン間ブレ
ークダウン電圧ＢＶｐｓはポリシリコン抵抗体（２）側
では保護されるＭＩＳトランジスタの保護ゲート耐圧約
１５Ｖより高く設定し、ゲート電極側では保護ゲート耐
圧より低く設定すると良い。In such an input protection circuit, a large input surge voltage can be connected to the ground on the side that is fully connected to the polysilicon resistor (2) with a large source-drain breakdown voltage BV□, and a small input surge voltage can be connected to a small source-drain breakdown voltage BV□. The input surge voltage can be uniformly distributed to the protection MIS transistor by the magnitude of the source-drain breakdown voltage BVDS.From this, the source of the protection MIS transistor The drain-to-drain breakdown voltage BVps is preferably set higher than the protection gate breakdown voltage of about 15 V on the polysilicon resistor (2) side, and lower than the protection gate breakdown voltage on the gate electrode side.

なお保護用ＭＩＳトランジスタのドレイン領域（６）の
ＰＮ接合破壊を防止するため、保護用ＭＩＳトランジス
タのソースドレイン間ブレークダウン電圧ＢＶａｓはＰ
Ｎ接合耐圧の約３０Ｖ以下に設計しなくてはならない。Note that in order to prevent PN junction breakdown in the drain region (6) of the protective MIS transistor, the source-drain breakdown voltage BVas of the protective MIS transistor is set to P.
It must be designed to have an N junction breakdown voltage of approximately 30V or less.

なお衛士した実施例ではへ！ゲート構造の保護用ＭＩＳ
トランジスタで説明したが、Ｓｉゲート構造のものでも
当然本発明の目的を達成できる。In addition, here is an example of a samurai! MIS for protection of gate structure
Although the description has been made using a transistor, it is obvious that the object of the present invention can also be achieved with a transistor having a Si gate structure.

（ト）発明の効果 本発明に依れば保護用ＭＩＳトランジスタのチャンネル
長りを漸減することによりソースドレイン間ブレークダ
ウン電圧ＢＶ、、を漸減できるので、入力サージ電圧を
保護用ＭＩＳトランジスタのチャンネルに均一に分散で
きる。このため大きい入力サージ電圧でも小きい入力サ
ージ電圧でも安定してＭＩＳトランジスタのゲート酸化
膜を保護できる。(G) Effects of the Invention According to the present invention, by gradually decreasing the channel length of the protective MIS transistor, the source-drain breakdown voltage BV can be gradually reduced, so that the input surge voltage can be applied to the channel of the protective MIS transistor. Can be dispersed evenly. Therefore, the gate oxide film of the MIS transistor can be stably protected even at large input surge voltages or small input surge voltages.

また本発明ではポリシリコン抵抗体（２）を用いるので
拡散抵抗体に比べて小さい面積で同一抵抗値を実現でき
、入力保護回路の小型化に寄与できる。Furthermore, since the present invention uses a polysilicon resistor (2), the same resistance value can be achieved with a smaller area than a diffused resistor, contributing to miniaturization of the input protection circuit.

更に本発明では入力サージ電圧を分散して保護用ＭＩＳ
トランジスタでグランドに抜くので、保護用ＭＩＳトラ
ンジスタが大きい入力サージ電圧で破壊されるおそれが
少なく、極めて破壊強度に強い入力保護回路を実現でき
る。Furthermore, in the present invention, the input surge voltage is distributed to protect the MIS.
Since the transistor is connected to the ground, there is little risk that the protective MIS transistor will be destroyed by a large input surge voltage, making it possible to realize an input protection circuit that is extremely resistant to destruction.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に依る入力保護回路を説明する上面図、
第２図は本発明の入力保護回路の等価回路図、第３図は
本発明の詳細な説明するための特性図、第４図および第
６図は従来の入力保護回路を説明する上面図、第５図お
よび第７図は第４図および第６図の従来の入力保護回路
の等価回路図である。 主な図番の説明 （１）は入力バッド、　（２）はポリシリコン抵抗体、
　　（４）は保護用ＭＩＳ）−ランジスタ、　（５）（
６）はソースドレイン領域、（７）はチャンネル領域で
ある。 出願人　三洋電機株式会社　外１名 代理人　弁理士　　佐　野　静　夫 第１図 第３図 ３ｖＤＳ ＋、ａｍ）FIG. 1 is a top view illustrating an input protection circuit according to the present invention;
FIG. 2 is an equivalent circuit diagram of the input protection circuit of the present invention, FIG. 3 is a characteristic diagram for explaining the present invention in detail, and FIGS. 4 and 6 are top views for explaining the conventional input protection circuit. FIGS. 5 and 7 are equivalent circuit diagrams of the conventional input protection circuits shown in FIGS. 4 and 6. Explanation of the main drawing numbers (1) is the input pad, (2) is the polysilicon resistor,
(4) is a protective MIS) - transistor, (5) (
6) is a source/drain region, and (7) is a channel region. Applicant: Sanyo Electric Co., Ltd. (1 person) and 1 other representative: Shizuo Sano (Figure 1, Figure 3, 3vDS +, am)

Claims (1)

【特許請求の範囲】[Claims] （１）入力パッドよりポリシリコン抵抗体および所定の
ソースドレイン間ブレークダウン電圧を有する保護用Ｍ
ＩＳトランジスタを介して保護されるＭＩＳトランジス
タのゲート電極に接続される入力保護回路に於て、前記
保護用ＭＩＳトランジスタのソースおよびドレイン領域
間のチャンネル長を前記ポリシリコン抵抗体に接続され
た側より減少させて前記ソースドレイン間ブレークダウ
ン電圧を減少させることを特徴とする入力保護回路。(1) A protective M with a polysilicon resistor and a predetermined source-drain breakdown voltage from the input pad.
In the input protection circuit connected to the gate electrode of the MIS transistor protected via the IS transistor, the channel length between the source and drain regions of the protection MIS transistor is determined from the side connected to the polysilicon resistor. An input protection circuit characterized in that the source-drain breakdown voltage is reduced by reducing the source-drain breakdown voltage.
JP13474985A 1985-06-20 1985-06-20 Input protecting circuit Pending JPS61292351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13474985A JPS61292351A (en) 1985-06-20 1985-06-20 Input protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13474985A JPS61292351A (en) 1985-06-20 1985-06-20 Input protecting circuit

Publications (1)

Publication Number Publication Date
JPS61292351A true JPS61292351A (en) 1986-12-23

Family

ID=15135676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13474985A Pending JPS61292351A (en) 1985-06-20 1985-06-20 Input protecting circuit

Country Status (1)

Country Link
JP (1) JPS61292351A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990015442A1 (en) * 1989-05-17 1990-12-13 David Sarnoff Research Center, Inc. Low voltage triggered snap-back device
US5043782A (en) * 1990-05-08 1991-08-27 David Sarnoff Research Center, Inc. Low voltage triggered snap-back device
US6208494B1 (en) 1998-04-20 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge
JP2002319629A (en) * 2000-11-01 2002-10-31 Seiko Instruments Inc Semiconductor device
JP2007281178A (en) * 2006-04-06 2007-10-25 Elpida Memory Inc Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494284A (en) * 1978-01-09 1979-07-25 Cho Lsi Gijutsu Kenkyu Kumiai Mis semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494284A (en) * 1978-01-09 1979-07-25 Cho Lsi Gijutsu Kenkyu Kumiai Mis semiconductor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990015442A1 (en) * 1989-05-17 1990-12-13 David Sarnoff Research Center, Inc. Low voltage triggered snap-back device
JPH05505062A (en) * 1989-05-17 1993-07-29 デイビッド　サーノフ　リサーチ　センター，インコーポレイテッド Snapback device triggered by low voltage
US5043782A (en) * 1990-05-08 1991-08-27 David Sarnoff Research Center, Inc. Low voltage triggered snap-back device
US6208494B1 (en) 1998-04-20 2001-03-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge
JP2002319629A (en) * 2000-11-01 2002-10-31 Seiko Instruments Inc Semiconductor device
JP4676116B2 (en) * 2000-11-01 2011-04-27 セイコーインスツル株式会社 Semiconductor device
JP2007281178A (en) * 2006-04-06 2007-10-25 Elpida Memory Inc Semiconductor device

Similar Documents

Publication Publication Date Title
US7859083B2 (en) Semiconductor device
US4893157A (en) Semiconductor device
EP2259316A3 (en) Semiconductor circuit with TFTs
JPS57141962A (en) Semiconductor integrated circuit device
CN1136367A (en) Input/output transistors with optimized ESD protection
GB1209271A (en) Improvements in semiconductor devices
JP2001274402A5 (en)
JPS61292351A (en) Input protecting circuit
US5321292A (en) Voltage limiting device having improved gate-aided breakdown
JPS61292352A (en) Input protecting circuit
JPS622648A (en) Input protecting circuit
JPS61292353A (en) Input protecting circuit
JP2006165481A (en) Semiconductor apparatus
KR930009127A (en) MOS transistor device and its manufacturing method
JPS61290751A (en) Input protective circuit
JP3204376B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
JPH0997844A (en) Semiconductor integrated circuit device
JPS62141754A (en) High-dielectric-strength semiconductor device
JPH0518467B2 (en)
JPH0669510A (en) High-breakdown-strength semiconductor device
JPH10125907A (en) Mos field-effect transistor with protective circuit
JPH02192170A (en) Semiconductor element
JPH04215468A (en) Static protective device
JP2624373B2 (en) Semiconductor device
JPH0685160A (en) Semiconductor integrated circuit device