JPS61292342A - Manufacture of multilayer interconnection structure - Google Patents

Manufacture of multilayer interconnection structure

Info

Publication number
JPS61292342A
JPS61292342A JP60104035A JP10403585A JPS61292342A JP S61292342 A JPS61292342 A JP S61292342A JP 60104035 A JP60104035 A JP 60104035A JP 10403585 A JP10403585 A JP 10403585A JP S61292342 A JPS61292342 A JP S61292342A
Authority
JP
Japan
Prior art keywords
film
aluminum
wiring
thick
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60104035A
Other languages
Japanese (ja)
Other versions
JPH0247102B2 (en
Inventor
Shunichi Fukuyama
俊一 福山
Yasuhiro Yoneda
泰博 米田
Masashi Miyagawa
昌士 宮川
Kota Nishii
耕太 西井
Azuma Matsuura
東 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60104035A priority Critical patent/JPS61292342A/en
Priority to US06/790,615 priority patent/US4670299A/en
Priority to KR1019850007985A priority patent/KR880000853B1/en
Priority to EP19900114892 priority patent/EP0406911B1/en
Priority to DE19853587041 priority patent/DE3587041T2/en
Priority to DE19853587442 priority patent/DE3587442T2/en
Priority to EP19850307905 priority patent/EP0198976B1/en
Publication of JPS61292342A publication Critical patent/JPS61292342A/en
Priority to KR1019870014659A priority patent/KR900005894B1/en
Priority to US07/281,926 priority patent/US4988514A/en
Publication of JPH0247102B2 publication Critical patent/JPH0247102B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

PURPOSE:To manufacture a multilayer interconnection structure having an insulating layer without disconnection and shortcircuit of wirings without crack at a resin film by forming one insulating layer as a double layer of an inorganic substance film on a silylated polymethylsilsesquioxane resin film. CONSTITUTION:An aluminum wiring layer 2 of 1mum thick is formed on a silicon substrate 1, and a thin polymethylsilsesquioxane silicide film of 1.2-1.4mum thick is formed thereon. The film 3 is formed by spin coating and thermal fusing to completely flatten the wiring step of aluminum of 1mum. Further, a phosphorus glass (PSG) film 4 of 1.0mum thick is formed by a CVD on the film 3. Then, to connect the first wiring layer with the second wiring layer, with a resist 5 as a mask a through hole 6 is formed with CF4 plasma, the resist 5 is removed by an oxygen plasma, an aluminum 2 of 1mum thick as the second wiring layer is deposited, and connected with the aluminum 2.

Description

【発明の詳細な説明】 〔概　要〕 多層配線構造体の導体配線層間の絶縁層を、シリル化ポ
リメチルシルセスキオキサン樹脂膜の上に無機物質膜を
形成した二重膜として形成し、これによって導体配線層
による段差を平坦化し、かつ配線の切断および短絡なら
びに絶縁層のクラック発生を防止する。[Detailed Description of the Invention] [Summary] An insulating layer between conductor wiring layers of a multilayer wiring structure is formed as a double film in which an inorganic material film is formed on a silylated polymethylsilsesquioxane resin film, This flattens the level difference caused by the conductive wiring layer, and prevents cutting and shorting of the wiring and cracking of the insulating layer.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体集積回路に使用する多層配線構造体に関
する。The present invention relates to a multilayer wiring structure used in a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

多層配線構造体の導体配線層間の絶縁層として、従来は
二酸化けい素、窒化けい素、アルミナ、リルガラスなど
の無機物質、またはポリイミド、シリコーンなどの樹脂
をそれぞれ単独で使用していた。Conventionally, inorganic substances such as silicon dioxide, silicon nitride, alumina, and lyrglass, or resins such as polyimide and silicone have been used alone as insulating layers between conductor wiring layers of multilayer wiring structures.

〔解決しようとする問題点〕[Problem to be solved]

蒸着またはＣＶ　Ｄ　（ｃｈｅｍｉｃａｌ　ｖａｐｏｒ
　ｄｉｐｏｓｉｔｉｏｎ）によって形成される無機物質
膜４は層厚が薄いので、第２図に示すように金属導体配
線２および上下配線接続部による段差がそのまま残され
る。従って絶縁層上の配線を微細化することが困難であ
り、配線の切断７および配線の短絡８を生じる問題があ
る。。Vapor deposition or CVD (chemical vapor)
Since the inorganic material film 4 formed by deposition is thin, the difference in level caused by the metal conductor wiring 2 and the upper and lower wiring connections remains as is, as shown in FIG. Therefore, it is difficult to miniaturize the wiring on the insulating layer, and there is a problem that disconnection 7 of the wiring and short circuit 8 of the wiring occur. .

スピンコードして２５０℃〜３５０℃に加熱し硬化させ
たポリイミドなどの耐熱性樹脂は膜厚が厚いので、第３
図に示すように、絶縁層３はその下の配線などによる段
差をかなり平坦化することができるが、この樹脂は５０
０℃において熱分解を開始すること、および吸湿しやす
い問題がある。Heat-resistant resins such as polyimide, which are spin-coded and cured by heating to 250°C to 350°C, have a thick film thickness, so
As shown in the figure, the insulating layer 3 can considerably flatten the level difference caused by the wiring underneath, but this resin
There are problems that thermal decomposition starts at 0°C and that it easily absorbs moisture.

有機溶剤に可溶なシリコーン樹脂もスピンコードして２
５０℃〜３５０℃に加熱し硬化させる。第３図に示すよ
うに樹脂膜３は段差をかなり平坦化することができ、か
つ窒素気流中で５００℃で１時間加熱しても熱分解は起
こらない。しかし、この樹脂膜３を通して上下配線２を
接続した後に、窓明は用マスクに使用したレジストを酸
素プラズマでアッシングするとき、または５００℃、１
時間の加熱後に膜厚１０μｍ程度に積層された部分の樹
脂層にクランクを発生する。Silicone resins that are soluble in organic solvents can also be spin-coded.
Heat to 50°C to 350°C to harden. As shown in FIG. 3, the resin film 3 can significantly flatten steps, and thermal decomposition does not occur even when heated at 500° C. for 1 hour in a nitrogen stream. However, after connecting the upper and lower wires 2 through this resin film 3, the window light is removed when the resist used for the mask is ashed with oxygen plasma or at 500°C.
After heating for a period of time, a crank is generated in the resin layer layered to a thickness of approximately 10 μm.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、基板上に導体配線層と絶縁層とを交互に
反復して形成し、この絶縁層によってその下に位置する
導体配線層による段差を平坦化することができる多層配
線構造体の製法であって、一つの絶縁層は、シリル化ポ
リメチルシルセスキオキサン樹脂膜３の上に無機物質膜
４を設けた二重膜として形成することを特徴とする多層
配線構造体の製法によって達成することができる。The above problem is solved by a multilayer wiring structure in which a conductor wiring layer and an insulating layer are alternately and repeatedly formed on a substrate, and this insulating layer can flatten the level difference caused by the conductor wiring layer located below. A manufacturing method for a multilayer wiring structure, characterized in that one insulating layer is formed as a double film in which an inorganic material film 4 is provided on a silylated polymethylsilsesquioxane resin film 3. can be achieved.

〔実施例と比較例〕[Example and comparative example]

実施例 第３図に示すように、（ａ）けい素基板ｌの上に膜厚Ｉ
Ｉｊｍのアルミニウム配線層２を形成し、（ｂ）その上
にシリル化ポリメチルシルセスキオキサンαＷ　＝３．
ＯＸ　１０’　、ＭＷ　／ＭＷ　＝１．２）の２０重量
％メチルイソブチルケトン溶液を４００Ｏｒｐｍでスピ
ンコードした。これを１２０℃で１０分間加熱して乾燥
させ、さらに３５０℃で１時間加熱して溶融させた。形
成された膜厚１．２〜１．４μｍのシリル化ポリメチル
シルセスキオキサン薄膜３は、スピンコードおよび加熱
溶融により、１μｍのアルミニウムの配線段差を完全に
平坦化した。（Ｃ１さらにこの薄膜３の上に膜厚１，０
μｍのりんガラス（Ｐ　Ｓ　Ｇ）膜４をＣＶＤにより形
成した。（ｄ１次に第一配線層と、第二配線層との接続
を行うために商品名ＡＺ１３５０レジスト５をマスクと
してＣＦ。Embodiment As shown in FIG. 3, (a) a film with a thickness I
An aluminum wiring layer 2 of Ijm is formed, and (b) silylated polymethylsilsesquioxane αW =3.
A 20% by weight solution of OX 10' , MW /MW = 1.2) in methyl isobutyl ketone was spin coded at 400 Orpm. This was heated at 120° C. for 10 minutes to dry it, and further heated at 350° C. for 1 hour to melt it. The formed silylated polymethylsilsesquioxane thin film 3 having a thickness of 1.2 to 1.4 μm completely flattened the 1 μm aluminum wiring level difference by spin cord and heat melting. (C1 Furthermore, on this thin film 3, a film thickness of 1,0
A phosphor glass (PSG) film 4 of μm thickness was formed by CVD. (d1 Next, perform CF using the product name AZ1350 resist 5 as a mask to connect the first wiring layer and the second wiring layer.

プラズマによりスルホール６を形成し、（ｅ）酸素プラ
ズマによりレジスト５の除去を行い、（ｆ）さらに第二
配線層とする膜厚１μｍのアルミニウム２を蒸着して第
一配線層のアルミニウム２と接続させた。このようにし
て形成した多層配線構造体は第４図の曲″４ＭＡに示す
ように電圧２５Ｖをかけてもリーク電流は観測されなか
った。また、２５０℃で５００時間放置後に、−６５℃
〜１５０℃の温度サイクルを５００時間（１サイクル９
０分）行なった信顛性試験の後も２５Ｖにおけるリーク
電流は観測されなかった。Through holes 6 are formed by plasma, (e) the resist 5 is removed by oxygen plasma, and (f) aluminum 2 with a thickness of 1 μm is further deposited to form the second wiring layer and connected to the aluminum 2 of the first wiring layer. I let it happen. In the multilayer wiring structure thus formed, no leakage current was observed even when a voltage of 25 V was applied as shown in the track "4MA" in FIG.
~150℃ temperature cycle for 500 hours (1 cycle 9
No leakage current at 25V was observed after the reliability test performed (0 minutes).

此ｌピ江上、 実施例の工程（ｂｌを行なわないことの他は実施例と同
様にして、第一配線層と第二配線層との間に膜厚１．０
μｍのりんガラス膜４をＣＶＤにより形成して多層配線
構造体を製造した。実施例と同様に電圧−リーク電流曲
線Ｂを求めた結果、１３Ｖで１ｍＡに近いリーク電流を
示した。On this page, the steps of the example (except that BL was not performed) were carried out in the same manner as in the example, and a film thickness of 1.0 was formed between the first wiring layer and the second wiring layer.
A multilayer wiring structure was manufactured by forming a μm thick phosphor glass film 4 by CVD. As a result of obtaining the voltage-leakage current curve B in the same manner as in the example, a leakage current close to 1 mA was shown at 13V.

工較斑主 りんガラス膜４を蒸着により形成したことの他は比較例
１と同様にして多層配線構造体を製造した。電圧−リー
ク電流曲線Ｃは１０Ｖで１ｍＡを超えるリーク電流を示
した。A multilayer wiring structure was manufactured in the same manner as in Comparative Example 1 except that the uneven phosphor glass film 4 was formed by vapor deposition. Voltage-leakage current curve C showed a leakage current of more than 1 mA at 10V.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、樹脂膜にクラックを発生することなく
、また配線の切断および短絡を生じるこのない絶縁層を
有する多層配線構造体を製造することができる。According to the present invention, it is possible to manufacture a multilayer wiring structure having an insulating layer that does not cause cracks in the resin film and does not cause disconnection or short circuits in the wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の多層配線構造体の製造工程図であり、 第２図は無機物質のみを絶縁層とする多層配線構造体の
断面図であり、 第３図は樹脂のみを絶縁層とする多層配線構造体の断面
医である。 第４図は多層配線構造体の電圧−リーク電流の関係を示
すグラフである。Fig. 1 is a manufacturing process diagram of a multilayer wiring structure according to the present invention, Fig. 2 is a cross-sectional view of a multilayer wiring structure in which an insulating layer is made only of an inorganic substance, and Fig. 3 is a diagram showing a manufacturing process of a multilayer wiring structure in which an insulating layer is made only of an inorganic substance. This is a cross-sectional view of a multilayer wiring structure. FIG. 4 is a graph showing the relationship between voltage and leakage current of a multilayer wiring structure.

Claims (1)

【特許請求の範囲】[Claims] １、基板上に導体配線層と絶縁層とを交互に反復して形
成し、この絶縁層によってその下に位置する導体配線層
による段差を平坦化することができる多層配線構造体の
製法であって、一つの絶縁層は、シリル化ポリメチルシ
ルセスキオキサン樹脂膜（３）の上に無機物質膜（４）
を設けた二重膜として形成することを特徴とする多層配
線構造体の製法。1. A method for manufacturing a multilayer wiring structure in which conductive wiring layers and insulating layers are alternately and repeatedly formed on a substrate, and the insulating layer can flatten the level difference caused by the conductive wiring layer located below. One insulating layer consists of an inorganic material film (4) on a silylated polymethylsilsesquioxane resin film (3).
A method for producing a multilayer wiring structure, characterized in that it is formed as a double film provided with.
JP60104035A 1984-11-01 1985-05-17 Manufacture of multilayer interconnection structure Granted JPS61292342A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP60104035A JPS61292342A (en) 1985-05-17 1985-05-17 Manufacture of multilayer interconnection structure
US06/790,615 US4670299A (en) 1984-11-01 1985-10-23 Preparation of lower alkyl polysilsesquioxane and formation of insulating layer of silylated polymer on electronic circuit board
KR1019850007985A KR880000853B1 (en) 1984-11-01 1985-10-29 Process for the preparation of low alkyl polysilsesquioxane
DE19853587442 DE3587442T2 (en) 1984-11-01 1985-10-31 Process for the preparation of polysilsesquioxanes.
DE19853587041 DE3587041T2 (en) 1984-11-01 1985-10-31 METHOD FOR PRODUCING INSULATOR LAYERS FROM SILYLATED POLYSILESESQUIOXANES ON ELECTRONIC PRINTED CIRCUIT.
EP19900114892 EP0406911B1 (en) 1984-11-01 1985-10-31 Process for preparation of polysilsesquioxane
EP19850307905 EP0198976B1 (en) 1984-11-01 1985-10-31 Process for formation of insulating layer of silylated polysilsesquioxane on electronic circuit board
KR1019870014659A KR900005894B1 (en) 1984-11-01 1987-12-21 Manufacture of multilayer interconnection structure
US07/281,926 US4988514A (en) 1984-11-01 1988-12-02 Preparation of lower alkyl polysilsesquioxane and formation of insulating layer of silylated polymer on electronic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60104035A JPS61292342A (en) 1985-05-17 1985-05-17 Manufacture of multilayer interconnection structure

Publications (2)

Publication Number Publication Date
JPS61292342A true JPS61292342A (en) 1986-12-23
JPH0247102B2 JPH0247102B2 (en) 1990-10-18

Family

ID=14369970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60104035A Granted JPS61292342A (en) 1984-11-01 1985-05-17 Manufacture of multilayer interconnection structure

Country Status (1)

Country Link
JP (1) JPS61292342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8992806B2 (en) 2003-11-18 2015-03-31 Honeywell International Inc. Antireflective coatings for via fill and photolithography applications and methods of preparation thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8992806B2 (en) 2003-11-18 2015-03-31 Honeywell International Inc. Antireflective coatings for via fill and photolithography applications and methods of preparation thereof

Also Published As

Publication number Publication date
JPH0247102B2 (en) 1990-10-18

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