JPS61290555A - Cache system - Google Patents

Abstract

PURPOSE:To obtain a cache system which can control a degree of residence in a cache memory of the data block concerned, by constituting it so that an LRU set value which is applied to initialization or reregistration of an LRU value becomes variable. CONSTITUTION:In case of initializing or reregistering an LRU value, a microprocessor 27 refers to read/write commands from a host system 11 of a buffer memory 30, and decides whether CC2 of its cache control bits CC2-CC0 is '0' or not. In case when the CC2 is '0', a prescribed value is generated by shifting an LRU set value, supplied to a memory 35 through a bus 26, a driver receiver D/R 32, and a bus 31, and registered in an LRU counter field of an entry. In case of a directory searching, in the next time, this LR value is used, and accordingly, if CC1 and CC0 are set to '1' in advance, a degree of residence in a cache memory 33 can be made small, and if they are set to '0' in advance, the degree of residence can be made large. Accordingly, by combining CC1 and CC0, the degree of residence in the cache memory 33 of a data block can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a cache system that applies an LRU method to a cache block replacement algorithm.

[Technical background of invention! ! 4j In this type of cache system, when accessing a memory in response to a read/write request, a directory search is first performed to determine whether or not the target data exists in the cache memory. If the directory search results in a cache pit or mishit, an operation is performed to initialize or re-register the LRU value corresponding to the hit cache block or the cache block to be replaced to a fixed value, such as "O". .

If there is a miss at the time of a read request, the corresponding data 70 pieces are read from the memory and registered in the replacement target cache block (in the cache memory).

[Problems in the background art] As mentioned above, in the conventional cache system, the LRU
The setting value was fixed regardless of the data block registered in the cache memory. However, the usage frequency of data blocks registered in cache blocks varies depending on the file format. Therefore, the present inventors
In a conventional cache system in which the LRU setting value is fixed, when a data block that is infrequently used is registered in a -H cache block, the residency level of the same data block in the cache memory becomes higher than that of other frequently used data blocks. I came to realize that there was a risk that the file would become larger than the high file size, leading to a decrease in the hit rate of the cache memory.

[Object of the Invention] This invention has been made in view of the above circumstances, and its purpose is to make it possible to change the LRU setting value applied to initialization or re-registration of the LRUI, thereby making it possible to make the corresponding data block resident in the cache memory. The purpose of this invention is to provide a cache system that can control the degree of caching.

[Summary of the Invention] According to the present invention, a cache system is applied that applies an LRU method to a cache block replacement algorithm. The above system includes a directory memory with an LRU counter field in each entry, and an arbitrary LRU counter field.
A command issuing means for issuing a read/write command to which an RU setting value is added, a directory search means, and a registration means are provided. When a read/write command is issued by the command issuing means, the directory search means searches the directory memory in response to the command. The registration means registers the LRU setting value added to the read/write command in the LRU counter field of the bit entry of the directory memory or the entry corresponding to the cache block to be replaced, according to the search result of the directory search means.

[Embodiment of the Invention] FIG. 1 shows a block configuration of a cache system, for example, a disk cache system, according to an embodiment of the invention, and 20 is a magnetic disk control device. The magnetic disk control device 20 has a hard disk control circuit (hereinafter referred to as HDC) 21 that controls the magnetic disk device 10 . HDC21 is data line 2
2 and a first bus 2 consisting of a control line 23
4. Connected to the host system 11 via a driver/receiver (hereinafter referred to as D/R) 25. HDC2
1 is also connected to a second bus 26. The bus 26 includes a microprocessor 27 that controls the entire magnetic disk control device 20, a program memory 28 that stores a program (microprogram) for controlling the microprocessor 270, a work memory 29 that forms a work area for the microprocessor 21, and A buffer memory 30 is connected to absorb the difference in transfer speed between the magnetic disk device 10 and the host system 11.

31 is the third bus. The bus 31 is connected to the second bus 26 via a D/R (driver/receiver) 32. Connected to the bus 31 are a cache control circuit 34 which mainly performs data transfer control including control of the cache memory 33, and a directory memory 35. As shown in FIG. 2, each entry in the directory memory 35 includes a disk block number field indicating the number of the data block (disk block) registered in the cache memory 33, and an LRU value (8 pits).
and an LRU counter field indicating the LRU counter field. The number of entries in the directory memory 35 is the same as the cache memory 3.
3, and for example, 16 (16 levels) per column.

In this embodiment, the magnetic disk device 10 and the cache memory 33 are associated with each other with 64 sectors (one track) as one block. Another magnetic disk device! 1
The 0 area (disk area) is 64 sectors (1 disk)
Each column is divided into two columns, column 0 and column 1. Therefore, the column value is indicated by the seventh least significant bit of the disk logical address. Further, the disk block number is indicated by the remaining bits excluding the lower 7 bits of the disk logical address.

The LRU value read from the directory memory 35 at the time of directory search is set on the third bus 31.
The input of an RU counter (hereinafter referred to as CLRU) 36 and the output of a driver 37 are also connected. CL Rt
The output of J 36 and the input of driver 37 are connected to cache control circuit 34 . Also bus 3
1 includes the input port of the register file 38 and the comparison! 139's 8 inputs are also connected. The output port of the register file 38 is connected to the A input of the comparator 39, and the output port of the comparator 39 is connected to the cache control circuit 3.
Connected to 4.

The cache control circuit 34 outputs the contents of the C L RU 36 onto the bus 31 by the driver 37.
It is connected to the register file 38 so as to control the input of the LRU value) to the register file 38.

The output of a directory memory address counter (hereinafter referred to as CDMA) 40 that specifies the address of the directory memory 35 is connected to address port A of the directory memory 35, and the input of CDMA 4G is connected to the second bus 26. ing. The output of CD MA 40 is also connected to the input port of register file 41, and the output port of register file 41 is connected to second bus 26. Further, a control circuit 34 is connected to the register file 41 so that the cache control circuit 34 can control the register file 41 .

Next, the operation of one embodiment of the present invention will be explained.

Read/write commands, which are disk access requests from the host system 50, are sent to the D/R 25 and No. 24.
The command is transmitted to the HDC 21 via the HDC 21 and held in a command register (not shown) within the HDC 21. This lead/
As shown in Figure 3, the write command consists of a command code specifying operations such as read/write, and a logical address 2.
(MSB), logical address 1 and logical address 0 (
LSB) disk logical address, number of data blocks, and cache control pits CC2 to CC
It is a 6-byte instruction including each field of O.

The read/write command in the command register is read by the microprocessor 21 and stored in a predetermined area of the work memory 29. When the microprocessor 27 stores the read/write command (from the host system 40) in the work memory 29, it issues a seek command and sets it in the HDC 21 in accordance with the request. This results in H
The DC 21 controls the magnetic disk device 10 to seek a designated track. Further, in accordance with the read/write command, the microprocessor 27 reads the disk block number corresponding to the area (disk area) of the magnetic disk device 10 to be accessed and the LR whose value is O.
Set the U value in register file 38 via bus 2B, D/R 32 and bus 31. In addition, the microprocessor 27 locates the seventh pit from the lowest pit of the disk logical address (pit 6 of logical address 0 shown in FIG. 3), that is, the beginning of the area of the directory memory 35 (area of 16 entries) indicated by the column value. CD address
Set to M A 4G. Thus, the directory search cycle shown below is repeated 16 times.

In this directory search cycle, first the CD M
The (directory memory) address indicated by A 40 is set in the first predetermined position of the register file 41. Then, the CD MA 40 is sequentially counted up.

As a result, the directory memory 35 indicated by CDMA40
The directory information for the entry in bytes is transferred to bus 31.
is read out and supplied to the B input of the comparator 39. Also,
In synchronization with this, the information stored in the register file 38 is compared! It is supplied in bytes to the A input of I39. A comparator 39 compares the input contents of A and B. The result of the comparator 39, that is, the result of a comparison of the data block number (as a target) from the register file 38 and the (ll record) data block number from the directory memory 35 in byte units; The results of the comparison between the LRu value and the LRU value from the directory memory 35 are sequentially notified to the cache control circuit 34.

Also, L of the directory information supplied from the directory memory 35 to the eight comparators 39 via the bus 31
The RU value is loaded into CLRU3B and incremented by +1.

The cache control circuit 34 first determines whether or not a cache hit has been made based on the data block number comparison result of the comparator 39. If there is a cache hit, the cache control circuit 34 checks the (directory memory) address set in the first predetermined location of the register file 41 (the address indicating the starting position of the corresponding entry in the current directory search cycle). ) to the same file 41 by adding a hit flag indicating a hit.
the second predetermined position. Next, the cache control circuit 34 determines (the corresponding entry in the directory memory 35) the cache block to be replaced at that point in time based on the LRU value comparison result of the comparator 39. If the LRU value from the directory memory 35 is greater than or equal to the LRU value from the register file 38, the cache control circuit 34 temporarily determines that the cache block corresponding to the corresponding entry is the replacement target cache block. In this case, the cache control circuit 34 sets the (directory memory) address set in the first predetermined location of the register file 41 to the third predetermined location of the same file 41 .

In addition, the cache control circuit 34
The LRU value indicated by 6 (+1) is output from the driver 31 onto the bus 31, and the LR value in the register file 38 is
Update the U value to the LRU value on bus 31. Further, the cache control circuit 34 is connected to the (CLRU) on the bus 31.
36) is written to the corresponding entry in the directory memory 35, regardless of the comparison result of the comparator 39.

That is, in this embodiment, for each directory search cycle,
The LRU value in the corresponding entry in the directory memory 35 is set to 1.

The above is the directory search cycle, and by repeating this cycle 16 times (for 16 levels), the directory search corresponding to the read/write command is completed. At this time, if the cache block has been cached, the directory memory 35 corresponding to the cache block is stored in the second predetermined location of the register file 41.
The (starting) address of the entry is set. Further, in the third predetermined position of the register file 41, the (first M) address of the entry in the directory memory 35 having the largest LRU value in the designated column is set.

When the directory search is completed, the microprocessor 27 reads the contents of the second predetermined location of the register file 41 via the bus 26, and checks whether it was a cache hit or a miss. If there is a catch hit, or if a read operation is specified even if there is a miss, the read operation is specified by the contents (directory address) of the second predetermined location of the read register file 41. The LRU value in the entry of the directory memory 35 is initialized (or re-registered) as described below.

That is, when the microprocessor 27 initializes (or re-registers) the LRU value, it first refers to the read/write command from the host system 11 stored in the buffer 7 memory 30, and sets the cache control bit CG.
2 to determine whether CC2 of CGO is "0".

In this example, if cc2-“OIT, CC1, cco
is defined as LRU setting data. In the case of CC2-“0”, the microprocessor 27 selects CC1, c
Shift cO to the left by 6 pits to obtain LRU as shown in Figure 4.
Create setting values ccl (MSB), cco, O, O, 0°0, O, O (LSB), supply the same LRU setting values to the directory memory 35 via the bus 26, D/R 32 and bus 31, It is registered in the LRU counter field of the above-mentioned entry in the same memory 35.

This newly registered LRU setting value is used for the next directory search (LRU value comparison and setting to CLRU 36). Therefore, ccl
, by setting ccO to "1", the degree of residence of the corresponding data block in the cash memory 33 can be increased, and it becomes "0".
By setting it to , you can reduce the degree of co-residency. That is, cci
, cco can control the degree of residence of data blocks in the cache memory 33.

Note that the operation of accessing the cache memory 33 and the magnetic disk device 10 in response to a read/write command at the time of a cache hit or miss will not be described because it is not directly related to the gist of the present invention.

Although a disk cache system in which a copy of a magnetic disk is stored in a cache memory has been described above, the present invention can also be applied to a cache system in which a copy of a main memory is stored in a cache memory.

[Effects of the Invention] As detailed above, according to the present invention, LRUi[ in the corresponding entry in the directory memory can be initialized or re-registered to an arbitrary LRLJ setting value at the time of a cash hit or a miss. The degree of residence of data blocks in the cache memory can be controlled, and the cache hit rate can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a disk cache system according to an embodiment of the present invention, FIG. 2 is a diagram showing the entry configuration of the directory memory 35 shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the format of the read/write command to be executed, and FIG. 4 is a diagram showing the format of the LRU setting value. DESCRIPTION OF SYMBOLS 10... Magnetic disk device, 11-- Host system, 20... Magnetic disk 1iI1m device, 27...
Microprocessor, 33... Cache memory, 3
4... Cache control circuit, 35... Directory memory, 36... LRLJ counter (CLR
U), 39... Comparator. Figure 2 Figure 13 Figure 4 Written amendment 1, Indication of the case Patent Application No. 1983-133432 2, Name of the invention Cash system 3, Person making the amendment Relationship with the case Patent applicant (307) Toshiba Corporation ( and 1 other person) 4. Agent No. 17 Mori Pill 6, 1-26-5 Toranomon, Minato-ku, Tokyo.
The rLRU value is set to 1 on page 12, line 9 of correction target 7, content of correction (1) specification. ”, the rLRU value is increased by +1. ” he corrected. ■ On the 6th line of the 13th text of the specification, or on the 12th line of the same page, the phrase ``If...'' is replaced with ``If it were, the second register file 41 read above.'' The LRU value in the entry of the directory memory 35 specified by the contents (directory address) of the predetermined position of Initialize (or re-register) the LRU value in the entry in the directory memory 35 specified by the contents of
do. ” he corrected. (3) In the 14th line, page 14, line 13 of the specification, the phrase ``Kiki'deki,'' is corrected to ``It can be made small, J.'' (4) In the 14th line, page 14 of the specification, ``It can be made small.'' ” should be corrected to “It can be made larger.”

Claims (1)

[Claims] In a cache system that applies an LRU method to a cache block replacement algorithm, there is provided a directory memory in which each entry has an LRU counter field, and a command that issues a read/write command to which an arbitrary LRU setting value is added. means, a directory search means for searching the directory memory in response to a read/write command issued by the command issuing means, and search for a hit entry in the directory memory or a cache block to be replaced according to the search result of the directory search means. A cache system comprising: registration means for registering the LRU setting value in an LRU counter field of a corresponding entry.